ADS7945 Datasheet, PDF (30/49 Pages) Texas Instruments – 14-Bit, 2 MSPS, Dual-Channel, Differential/Single-Ended, Ultralow-Power Analog-to-Digital Converters

ADS7945
ADS7946
SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
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CS can be held low past the 16th falling edge of SCLK. The devices continue to output recently converted data
starting with the 16th SCLK falling edge. If CS is held low until the 30th SCLK falling edge, then the devices
detect 32-clock mode. Note that the device data from recent conversions are already output with no latency
before the 30th SCLK falling edge. Once 32-clock mode is detected, the device outputs 16 zeros during the next
conversion (in fact, for the first 16 clocks), unlike 16-clock mode where the devices output the previous
conversion result. SCLK can be stopped after the devices have seen the 30th falling edge with CS low.
CONVERSION ABORT
For some event triggered applications such as latching position of absolute position sensor on marker or homing
pulse, it is essential to abort ongoing conversion on event and quickly start fresh acquisition. ADS794X features
conversion abort function. CS high during conversion (during first 16 clocks) will abort ongoing conversion and
start fresh acquisition. Device will sample acquired signal during CS high period on falling edge of CS and will
start conversion normally, however data on SDO (conversion results from aborted frame) will not be valid.
For example if conversion is aborted during ‘n^th’ frame and (n+1) is first valid frame after conversion abort. SDO
data during frame number (n+1) (corresponding to n^th conversion) will not be valid. Conversion results for sample
and conversion during frame number (n+1) will be available in frame number (n+2).
POWER-DOWN
The ADS7945/6 devices offer an easy-to-use power-down feature available through a dedicated PDEN pin (pin
12). A high level on PDEN at the CS rising edge enables the power-down mode for that particular cycle.
Figure 83 to Figure 85 illustrate device operation with power-down in both 32-clock and 16-clock mode.
Many applications must slow device operation. For speeds below approximately 500 kSPS, it is convenient to
use 32-clock mode with power-down. This configuration results in considerable power savings.
As shown in Figure 83, PDEN is held at a logic '1' level. Note that the device looks at the PDEN status only at
the CS rising edge; however, for continuous low-speed operation, it is convenient to continuously hold PDEN = 1.
The devices detect power-down mode on the CS rising edge with PDEN = 1.
CS
SCLK
t _CONV
12
14 15 16 17 18 27 28 29 30 31 32
t _ACQ
t_ACQ(MIN)+
1 ms
SDO
Power-Down State
(Internal)
I_DYNAMIC
D13 D12 D3 D2 D1 D0
I_STATIC
I_AVDD Profile
IPD_DYNAMIC
IPD_STATIC if
SCLK is off,
otherwise
IPD_DYNAMIC.
Figure 83. Operation with a 32-Clock Frame in Power-Down Mode (PDEN = 1)
On the CS falling edge, the devices start normal operation as previously described. The devices complete
conversions on the 16th SCLK falling edge. The devices enter the power-down state immediately after
30
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