TPS53219A_15 Datasheet, PDF (3/35 Pages) Texas Instruments – Single Synchronous Step-Down Controller

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5 Pin Configuration and Functions
TPS53219A
SLUSAU4A – DECEMBER 2011 – REVISED DECEMBER 2015
RGT Package
16-Pin QFN With Exposed Thermal Pad
Top View
16 15 14 13
TRIP 1
EN 2
VFB 3
RF 4
TPS53219A
12 SW
11 DVRL
10 VDRV
9 VREG
5678
PIN
NAME
NO.
DRVH
13
DRVL
11
EN
2
GND
7
MODE
5
NC
15
PAD
–
PGOOD
16
PGND
8
RF
4
SW
12
TRIP
1
VBST
14
VDD
6
VDRV
10
VFB
3
VREG
9
TYPE ⁽¹⁾
Pin Functions
DESCRIPTION
O
High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is
defined by the voltage across VBST to SW node bootstrap flying capacitor.
O
Synchronous MOSFET driver output. The PGND referenced driver. The gate drive voltage is defined by
VDRV voltage.
I
Enable pin. Place a 1-kΩ resistor in series with this pin if the source voltage is higher than 5.5 V.
G
Ground pin. This is the ground of internal analog circuitry. Connect to GND plane at single point.
I
Soft-start and skip/CCM selection. Connect a resistor to select soft-start time using Table 1. The soft-
start time is detected and stored into internal register during start-up.
–
No connection.
–
Thermal pad. Use five vias to connect to GND plane.
O
Open-drain power good flag. Provides 1-ms start-up delay after the VFB pin voltage falls within specified
limits. When VFB goes out specified limits PGOOD goes low after a 2-µs delay.
G
Power ground. Connect to GND plane.
I
Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using
Table 2. The switching frequency is detected and stored during the start-up.
P
Output of converted power. Connect this pin to the output inductor.
OCL detection threshold setting pin. 10 µA at room temp, 4700 ppm/°C current is sourced and set the
I
OCL trip voltage as follows.
V_OCL = V_TRIP/8 spacer ( V_TRIP ≤ 3 V, V_OCL ≤ 375 mV)
P
Supply input for high-side FET gate driver (boost terminal). Connect a capacitor from this pin to SW-
node. Internally connected to VREG through bootstrap MOSFET switch.
P
Controller power supply input. The input range is from 4.5 V to 25 V.
I
Gate drive supply voltage input. Connect to VREG if using LDO output as gate drive supply.
I
Output feedback input. Connect this pin to V_OUT through a resistor divider.
O
6.2-V LDO output. This is the supply of internal analog circuitry and driver circuitry.
(1) I=Input, O=Output, P=Power, G=Ground
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