TPL5111 Datasheet, PDF (3/25 Pages) Texas Instruments – Nano-Power System Timer for Power Gating

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5 Pin Configuration and Functions
TPL5111
SNAS659A – JUNE 2015 – REVISED JULY 2015
DDC Package
6-Lead SOT-23
Top View
TPL5111
1
VDD
EN/
ONE_ SHOT
6
2
GND
DRVn
5
3
DELAY/
M_DRV
DONE
4
PIN
NO.
NAME
1
VDD
2
GND
3
DELAY/
M_DRV
4
DONE
5
DRVn
6
EN/
ONE_SHOT
TYPE ⁽¹⁾
P
G
I
I
O
I
Pin Functions
DESCRIPTION
Supply voltage
Ground
Time interval configuration (during
power on) and logic input for
manual Power ON
Logic Input for watchdog
functionality
Power Gating output signal
generated every t_IP
Select mode of operation
(1) G= Ground, P= Power, O= Output, I= Input.
APPLICATION INFORMATION
Resistance between this pin and GND is used to
select the time interval. The manual Power ON signal
(logic HIGH) can also connected to this pin.
Digital signal driven by the µC to indicate successful
processing.
The ENABLE pin of the LDO or DC-DC converter is
connected to this pin. DRVn is active HIGH.
When EN/ONE_SHOT = HIGH, the TPL5111 works
as a TIMER. When EN/ONE_SHOT = LOW, the
TPL5111 asserts DRVn one time for the
programmed time interval. In this mode, the DRVn
signal may be manually asserted by applying a logic
HIGH to the DELAY/M_DRV pin.
Copyright © 2015, Texas Instruments Incorporated
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