TP3064_11 Datasheet, PDF (3/20 Pages) Texas Instruments – Enhanced Serial Interface CMOS CODEC/Filter COMBO

Connection Diagrams
Dual-In-Line Package
Plastic Chip Carrier
Top View
TL H 5070–2
Pin Description
Symbol
VPO^a
GNDA
VPO^b
VPI
VF_RO
V_CC
FS_R
D_R
BCLK_R
CLKSEL
MCLK_R
PDN
Function
The non-inverted output of the receive power
amplifier
Analog ground All signals are referenced to
this pin
The inverted output of the receive power
amplifier
Inverting input to the receive power amplifier
Analog output of the receive filter
Positive power supply pin V_CCe a5Vg5%
Receive frame sync pulse which enables
BCLK_R to shift PCM data into D_R FS_R is an
8 kHz pulse train See Figures 2 and 3 for
timing details
Receive data input PCM data is shifted into
D_R following the FS_R leading edge
The bit clock which shifts data into D_R after
the FS_R leading edge May vary from 64 kHz
to 2 048 MHz Alternatively may be a logic
input which selects either
1 536 MHz 1 544 MHz or 2 048 MHz for
master clock in synchronous mode and
BCLK_X is used for both transmit and receive
directions (see Table I)
Receive master clock Must be 1 536 MHz
1 544 MHz or 2 048 MHz May be
asynchronous with MCLK_X but should be
synchronous with MCLK_X for best
performance When MCLK_R is connected
continuously low MCLK_X is selected for all
internal timing When MCLK_R is connected
continuously high the device is powered
down
2
Top View
TL H 5070 – 6
Order Number TP3064J or TP3067J
See NS Package J20A
Order Number TP3064WM or TP3067WM
See NS Package M20B
Order Number TP3064N or TP3067N
See NS Package N20A
Order Number TP3064V or TP3067V
See NS Package V20A
Symbol
MCLK_X
BCLK_X
D_X
FS_X
TS_X
ANLB
GS_X
VF_XI^b
VF_XI^a
V_BB
Function
Transmit master clock Must be 1 536 MHz
1 544 MHz or 2 048 MHz May be
asynchronous with MCLK_R Best
performance is realized from synchronous
operation
The bit clock which shifts out the PCM data
on D_X May vary from 64 kHz to 2 048 MHz
but must be synchronous with MCLK_X
The TRI-STATE PCM data output which is
enabled by FS_X
Transmit frame sync pulse input which
enables BCLK_X to shift out the PCM data on
D_X FS_X is an 8 kHz pulse train see Figures 2
and 3 for timing details
Open drain output which pulses low during
the encoder time slot
Analog Loopback control input Must be set
to logic ‘0’ for normal operation When pulled
to logic ‘1’ the transmit filter input is
disconnected from the output of the transmit
preamplifier and connected to the VPO^a
output of the receive power amplifier
Analog output of the transmit input amplifier
Used to externally set gain
Inverting input of the transmit input amplifier
Non-inverting input of the transmit input
amplifier
Negative power supply pin V_BBeb5Vg5%