TLK4211EA Datasheet, PDF (3/17 Pages) Texas Instruments – 4.25 Gbps Cable and PC Board Equalizer

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RGT PACKAGE
(TOP VIEW)
VCC
DIN+
DIN−
VCC
16 15 14 13
1
12
2
11
EP
3
10
4
9
5678
VCC
DOUT+
DOUT−
OUTPOL
TLK4211EA
SLLS655 – NOVEMBER 2005
P0019-02
Figure 2. Pin Out of TLK4211EA in a 3 mm × 3 mm 16-Pin QFN Package
TERMINAL
NAME
NO.
VCC
1, 4 , 12
DIN+
2
DIN–
3
NC
5, 7, 13
DISABLE
6
GND
8, 16
OUTPOL
9
DOUT–
10
DOUT+
11
COC1
14
COC2
15
EP
EP
TERMINAL FUNCTIONS
TYPE
DESCRIPTION
Supply
Analog in
Analog in
CMOS in
Supply
CMOS in
CML out
CML out
Analog
Analog
3.3-V ±10% supply voltage
Non-inverted data input. On-chip 100-Ω terminated to DIN–
Inverted data input. On-chip 100-Ω terminated to DIN+
Not connected
Disables CML output stage when set to high level
Circuit ground.
Output data signal polarity select (internally pulled up):
Setting to high-level or leaving pin open selects normal polarity.
Low-level selects inverted polarity.
Inverted data output. On-chip 50-Ω back-terminated to VCC.
Non-inverted data output. On-chip 50-Ω back-terminated to VCC.
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this
pin and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins
14 and 15).
Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this
pin and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins
14 and 15).
Exposed die pad (EP) must be grounded.
3