THS8134_14 Datasheet, PDF (3/26 Pages) Texas Instruments – TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER

THS8134, THS8134A, THS8134B
TRIPLE 8ĆBIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRIĆLEVEL SYNC GENERATION
SLVS205D − MAY 1999 − REVISED MARCH 2000
Terminal Functions (Continued)
TERMINAL
NAME
I/O
PIN
DESCRIPTION
M2
48
I Operation mode control 2. The second rising edge on CLK after a transition on SYNC latches M2. The
interpretation is dependent on the polarity of the last SYNC transition:
SYNC L to H: latched as M2_INT
SYNC H to L: latched as INS3_INT
Together with M1, M2_INT configures the device as shown in Table 1. When INS3_INT is high, the sync output is
inserted on all DAC outputs; a low will insert it only on the AGY output. See also Figure 2 and Table 2. The value of
M2 at power-up is undetermined. Therefore at least 1 L → H transition on SYNC is required to set M2.
NC
9, 10,
Not connected
13, 14,
35, 36
RPr0−RPr7 15−22 I Red or Pr pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for different
operating modes.
SYNC
24
I Sync control input, active low. A rising edge on CLK latches SYNC. When asserted, only the AGY output
(INS3_INT=L, see terminal M2) or ARPr, AGY and ABPb outputs (INS3_INT=H, see terminal M2) are driven to
the sync level, irrespective of the values on the data or BLANK inputs. Consequently, SYNC should remain low
for the whole duration of sync, which is in the case of a tri-level sync both the negative and positive portion (see
Figure 7).
SYNC_T
25
I Sync tri-level control, active high. A rising edge on CLK latches SYNC_T. When asserted, a positive sync (higher
than blanking level) is generated when SYNC is low. When disabled, a negative sync (lower than blanking level)
is generated when SYNC is low. When generating a tri-level (negative-to-positive) sync, a L → H transition on
this signal positions the start of the positive transition. See Figure 6 for timing control.
The value on SYNC_T is ignored when SYNC is not asserted (high).
VREF
37 I/O Voltage reference for DACs. An internal voltage reference of nominally 1.35 V is provided, which requires an
external 0.1 µF ceramic capacitor between VREF and AVSS. However, the internal reference can be overdriven
by an externally supplied reference voltage.
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