SN74LVC2G80_16 Datasheet, PDF (3/18 Pages) Texas Instruments – Dual Positive-Edge-Triggered D-Type Flip-Flop

SN74LVC2G80
www.ti.com
SCES309F – DECEMBER 2001 – REVISED DECEMBER 2013
Recommended Operating Conditions⁽¹⁾
MIN
MAX UNIT
V_CC
Supply voltage
Operating
Data retention only
1.65
5.5
V
1.5
V_IH
High-level input voltage
V_IL
Low-level input voltage
V_I
Input voltage
V_O
Output voltage
I_OH
High-level output current
V_CC = 1.65 V to 1.95 V
V_CC = 2.3 V to 2.7 V
V_CC = 3 V to 3.6 V
V_CC = 4.5 V to 5.5 V
V_CC = 1.65 V to 1.95 V
V_CC = 2.3 V to 2.7 V
V_CC = 3 V to 3.6 V
V_CC = 4.5 V to 5.5 V
V_CC = 1.65 V
V_CC = 2.3 V
V_CC = 3 V
0.65 × V_CC
1.7
V
2
0.7 × V_CC
0.35 × V_CC
0.7
V
0.8
0.3 × V_CC
0
5.5 V
0
V_CC
V
–4
–8
–16 mA
–24
I_OL
Low-level output current
V_CC = 4.5 V
V_CC = 1.65 V
V_CC = 2.3 V
V_CC = 3 V
–32
4
8
16 mA
24
Δt/Δv Input transition rise or fall rate
T_A
Operating free-air temperature
V_CC = 4.5 V
V_CC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
V_CC = 3.3 V ± 0.3 V
V_CC = 5 V ± 0.5 V
32
20
10 ns/V
5
–40
125 °C
(1) All unused inputs of the device must be held at V_CC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2001–2013, Texas Instruments Incorporated
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