SN74LVC2G66-Q1_14 Datasheet, PDF (3/19 Pages) Texas Instruments – DUAL BILATERAL ANALOG SWITCH

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SN74LVC2G66-Q1
SCES829A – JUNE 2011 – REVISED JULY 2012
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
SN74LVC2G66-
Q1
DCU
UNIT
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
8 PINS
204.4
77
83.2
7.1
82.7
N/A
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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RECOMMENDED OPERATING CONDITIONS⁽¹⁾
MIN
MAX UNIT
V_CC
Supply voltage
V_I/O
I/O port voltage
V_IH
High-level input voltage, control input
V_IL
Low-level input voltage, control input
V_I
Control input voltage
Δt/Δv Input transition rise/fall time
T_A
Operating free-air temperature
V_CC = 1.65 V to 1.95 V
V_CC = 2.3 V to 2.7 V
V_CC = 3 V to 3.6 V
V_CC = 4.5 V to 5.5 V
V_CC = 1.65 V to 1.95 V
V_CC = 2.3 V to 2.7 V
V_CC = 3 V to 3.6 V
V_CC = 4.5 V to 5.5 V
V_CC = 1.65 V to 1.95 V
V_CC = 2.3 V to 2.7 V
V_CC = 3 V to 3.6 V
V_CC = 4.5 V to 5.5 V
1.65
0
V_CC × 0.65
V_CC × 0.7
V_CC × 0.7
V_CC × 0.7
0
–40
5.5
V_CC
V_CC × 0.35
V_CC × 0.3
V_CC × 0.3
V_CC × 0.3
5.5
20
20
10
10
125
V
V
V
V
V
ns/V
°C
(1) Hold all unused inputs of the device at V_CC or GND to ensure proper device operation. See the TI application report, Implications of
Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2011–2012, Texas Instruments Incorporated
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