PTB48580A Datasheet, PDF (3/13 Pages) Texas Instruments – Dual Complementary-Output DC/DC Converter for DSL

PTB48580A
Dual Complementary-Output
DC/DC Converter for DSL
Not Recommended for New Designs
SLTS240 DECEMBER 2004
Specifications (Unless otherwise stated, T_A =25°C, V_I =48 V, C_I =0 µF, ±C_O =0 µF, |+I_O | = |–I_O |, and |±I_O | =0.5 |±I_O |max)
PTB48580A
Characteristic
Symbol
Conditions
Min
Typ
Max
Units
Output Power
Output Current
Output Load Imbalance
Output Voltage
Temperature Variation
Line Regulation
Load Regulation
Efficiency
V_o Ripple (pk-pk)
Transient Response
Over Current Threshold
P_O
Total output power from ±V_O
0
—
|±I_O |
Over V_I range, |+I_O | – |–I_O | ≤ 0.1 A
0
—
|+I_O | – |–I_O |
|+I_O | ≥0.1 A, |–I_O | ≥ 0.1 A
0
—
|±V_O |
Inlcudes
–40 ≤T_A
set-point,
≤+85°C
line,
|+I_O
|
–
|–I_O
|
≤
0.1
A
4.75 ⁽²⁾
5
∆Reg_temp
–40 ≤T_A ≤ +85°C, |±I_O | =0.1 A
±V_O
—
±1
∆Reg_line
Over V_I range, balanced load
±V_O
—
±0.1
∆Reg_load
Over ±I_O range, balanced load
±V_O
—
±0.2
η
P_O =P_O max
—
86
±Vr
20 MHz bandwidth,
C_O =10 µF tantalum capacitor
—
25
t_S
0.1 A/µs load step, 50% to 75% ±I_O max
—
30
∆V_O pk
|±V_O| over/undershoot
—
±1
I_Otrip
V_I =36 V
reset followed by auto-recovery
3.3
4.3
30 ⁽¹⁾
3 ⁽²⁾
1 ⁽³⁾
5.25 ⁽²⁾
—
±0.4
±0.4
—
50 ⁽⁴⁾
—
—
5.3
W
A
A
V
%V_O
%V_O
%V_O
%
mV_pp
µs
%V_O
A
Short Circuit Current
Output Voltage Adjust Range
Switching Frequency
Under-Voltage Lockout
On/Off Enable (pin 3)
Input High Voltage
Input Low Voltage
Input Low Current
Standby Input Current
Start-up Time
Internal Input Capacitance
External Output Capacitance
Reliability
|±V_O | adj
ƒ_S
VV^IIoofnf
V_IH
V_IL
I_IL
I_I standby
t_ON
C_I
C_O
MTBF
Continuous over-current trip,
|±I_O |_PK
—
|+I_O | = |–I_O |
Duty —
|+V_O | and |–V_O | adjust simulataneously
3.5
Over V_I and I_O ranges
440
VV_II
increasing
decreasing
—
—
Referenced to –V_I (pin 4)
+3.6
–0.2
—
pin 3 open circuit
—
|±I_O | =1 A, |±V_O | rising 0 to 0.95 |±V_O | _TYP
—
—
Capacitance from either output to COM (pin 6)
0
Per Telcordia SR-332
50% stress, T_A =40°C, ground benign
2.8
6.5
10
—
470 ⁽⁶⁾
33
32
—
—
—
2
10
2
—
—
—
—
6 ⁽⁵⁾
500
—
—
+75 ⁽⁷⁾
+0.8
–1
—
—
—
2,000 ⁽⁸⁾
—
A
%
V
kHz
V
V
mA
mA
ms
µF
µF
10⁶ Hrs
Notes: (1) See Safe Operating Area curves or contact the factory for the appropriate derating.
(2) Under balanced load conditions, load current flowing out of +V_O is balanced to within ±0.1 A of that flowing into –V_O .
(3) A load imbalance is the difference in current flowing from +V_O to –V_O . The module can operate with a higher imbalance but with reduced specifications.
(4) Output voltage ripple is measured with a 10 µF tantalum capacitor connected from +V_O (pin 5) or –V_O (pin 8), to COM (pin 6).
(5) When the output voltage is adjusted higher than the nominal output voltage the load current must not exceed the module’s maximum power rating.
(6) This is the free-running frequency. The module can be made to synchronize with the PTB48500 when both modules are used together in a system.
(7) The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is diode protected
and may be connected to +V_I . The open-circuit voltage is 7 V max. If it is left open circuit the converter will operate when input power is applied.
(8) Electrolytic capacitors with very low equivalent series resistance (ESR) may induce instability when used on the output. Consult the factory before using
capacitors with organic, or polymer-aluminum type electrolytes.
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