OPA211-EP Datasheet, PDF (3/23 Pages) Texas Instruments – 1.1nV/√Hz NOISE, LOW POWER, PRECISION OPERATIONAL AMPLIFIER

OPA211-EP
www.ti.com
SBOS638 – JUNE 2012
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Over operating free-air temperature range (unless otherwise noted).
Supply Voltage
Input Voltage
Input Current (Any pin except power-supply pins)
Output Short-Circuit⁽²⁾
Operating Temperature
Storage Temperature
Junction Temperature
ESD Ratings
Human Body Model (HBM)
Charged Device Model (CDM)
V_S = (V+) – (V–)
(T_A)
(T_A)
(T_J)
VALUE
40
(V–) – 0.5 to (V+) + 0.5
±10
Continuous
–55 to +125
–65 to +150
200
3000
1000
UNIT
V
V
mA
°C
°C
°C
V
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Short-circuit to V_S/2 (ground in symmetrical dual supply setups), one amplifier per package.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
OPA211
DGK
UNITS
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
8 PINS
184.9
71.2
104.9
11.5
103.4
N/A
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): OPA211-EP
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