LMX2485Q-Q1 Datasheet, PDF (3/50 Pages) Texas Instruments – Low Power Dual PLLatinum Frequency Synthesizers

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5 Pin Configuration and Functions
RTW Package
24-Pin WQFN
Top View
LMX2485Q-Q1
SNOSCP7A – MARCH 2013 – REVISED JANUARY 2016
CPoutRF 1
GND 2
VddRF1 3
FinRF 4
FinRF* 5
LE ₆
24 23 22 21 20 19
Pin 0
(Ground Substrate)
18 OSCout
17 VddIF2
16 CPoutIF
15 GND
14 VddIF1
13 FinIF
7 8 9 10 11 12
NAME
CE
PIN
NO.
10
CLK
8
CPoutIF
16
CPoutRF
1
DATA
7
ENOSC
19
FinIF
13
FinRF
4
FinRF*
5
FLoutRF
23
Ftest/LD
12
GND
0
GND
2
GND
15
LE
6
NC
21
OSCin
20
OSCout
18
VddRF1
3
VddRF2
9
VddRF3
22
VddRF4
24
VddIF1
14
VddIF2
17
Pin Functions
I/O
DESCRIPTION
I
Chip Enable control pin. Must be pulled high for normal operation.
I
MICROWIRE Clock. High-impedance CMOS Clock input. Data for the various counters is
clocked into the 24 bit shift register on the rising edge
O
IF PLL charge pump output
O
RF PLL charge pump output.
I
MICROWIRE Data. High-impedance binary serial data input.
I
Oscillator enable. When this is set to high, the OSCout pin is enabled regardless of the state
of other pins or register bits.
I
IF PLL high-frequency input pin.
I
RF PLL high-frequency input pin.
I
RF PLL complementary high-frequency input pin. Shunt to ground with a 100-pF capacitor.
O
RF PLL Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
O
Test frequency output / Lock Detect.
—
Ground Substrate. This is on the bottom of the package and must be grounded.
—
RF PLL analog ground.
—
IF PLL digital ground.
I
MICROWIRE Load Enable. High impedance CMOS input. Data stored in the shift registers is
loaded into the internal latches when LE goes HIGH
I
This pin must be left open.
I
Input for TCXO signal.
O
Buffered output of the OSCin signal.
—
RF PLL analog power supply.
—
Power supply for RF PLL digital circuitry.
—
Power supply for RF PLL digital circuitry.
—
RF PLL analog power supply.
—
IF PLL analog power supply.
—
IF PLL power supply.
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