LMK02000 Datasheet, PDF (3/24 Pages) National Semiconductor (TI) – Precision Clock Conditioner with Integrated PLL

LMK02000
www.ti.com
Pin #
32
34, 35
36
38, 39
41, 42
44, 45
47, 48
DAP
SNAS390D – NOVEMBER 2006 – REVISED SEPTEMBER 2007
Pin Descriptions (continued)
Pin Name
CPout
Fin, Fin*
Bias
CLKout4, CLKout4*
CLKout5, CLKout5*
CLKout6, CLKout6*
CLKout7, CLKout7*
DAP
I/O
Description
O Charge Pump Output
I Frequency Input; Must be AC coupled
I Bias Bypass
O LVPECL Clock Output 4
O LVPECL Clock Output 5
O LVPECL Clock Output 6
O LVPECL Clock Output 7
- Die Attach Pad is Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings ^(1)(2)(3)
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature Range
Lead Temperature (solder 4 s)
Junction Temperature
Symbol
V_CC
V_IN
T_STG
T_L
T_J
Ratings
-0.3 to 3.6
-0.3 to (V_CC + 0.3)
-65 to 150
+260
125
Units
V
V
°C
°C
°C
(1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD
protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Ambient Temperature
Power Supply Voltage
T_A
-40
25
V_CC
3.15
3.3
Max
Units
85
°C
3.45
V
Package Thermal Resistance
Package
48-Lead WQFN ⁽¹⁾
θ_JA
27.4° C/W
θ_{J-PAD (Thermal Pad)}
5.8° C/W
(1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These
vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in
the board layout.
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