LMK01000_14 Datasheet, PDF (3/27 Pages) Texas Instruments – 1.6 GHz High Performance Clock Buffer, Divider, and Distributor

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Connection Diagram
LMK01000
SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009
Figure 1. 48-Pin LLP Package
48 47 46 45 44 43 42 41 40 39 38 37
GND
1
NC
2
Vcc1
3
CLKPWire
4
DATAPWire
5
LEPWire
6
NC
7
Vcc2
8
NC
9
NC 10
GOE 11
Test 12
LLP-48
Top Down View
DAP
36 Bias
35 CLKin1*
34 CLKin1
33 Vcc10
32 NC
31 Vcc9
30 Vcc8
29 CLKin0*
28 CLKin0
27 SYNC*
26 Vcc7
25 GND
13 14 15 16 17 18 19 20 21 22 23 24
Pin Functions
Pin #
1, 25
2, 7, 9,10, 32
3, 8, 13, 16, 19, 22, 26,
30, 31, 33, 37, 40, 43, 46
4
5
6
11
12
14, 15
17, 18
20, 21
23, 24
27
Pin Descriptions
Pin Name
I/O
GND
-
NC
-
Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8,
Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14
-
CLKuWire
I
DATAuWire
I
LEuWire
I
GOE
I
Test
O
CLKout0, CLKout0*
O
CLKout1, CLKout1*
O
CLKout2, CLKout2*
O
CLKout3, CLKout3*
O
SYNC*
I
Description
Ground
No Connect. Pin is not connected to the die.
Power Supply
MICROWIRE Clock Input
MICROWIRE Data Input
MICROWIRE Latch Enable Input
Global Output Enable
This is an output pin used strictly for test purposes
and should be not connected for normal operation.
However, any load of an impedance of more than 1
kΩ is acceptable.
Clock Output 0
Clock Output 1
Clock Output 2
Clock Output 3
Global Clock Output Synchronization
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