DS91C176_14 Datasheet, PDF (3/20 Pages) Texas Instruments – 100 MHz Single Channel M-LVDS Transceivers

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Connection and Logic Diagram
DS91C176, DS91D176
SNLS146K – MARCH 2006 – REVISED NOVEMBER 2009
Figure 1. Top View
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, V_ID/2. A type 2 receiver has a built
in offset that is 100mV greater than V_ID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
Type 1
Type 2
2.4 V
xxxxxxxx High
V_ID
High
150 mV
50 mV
0V
-50 mV
Low
Low
-2.4 V
Transition Region
Figure 2. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2006–2009, Texas Instruments Incorporated
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