DS25BR204_15 Datasheet, PDF (3/21 Pages) Texas Instruments – 3.125 Gbps 1:4 LVDS Repeater with Transmit Pre-Emphasis and Receive Equalization

DS25BR204
www.ti.com
Pin Name
IN1+, IN1-,
IN2+, IN2-,
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
EQ1, EQ2,
PE0, PE1,
PE2, PE3
SEL_in
LOS2
LOS1
PWDN0,
PWDN1,
PWDN2,
PWDN3
NC
PWDN
VDD
GND
Pin
Number
4, 5,
6, 7,
29, 28,
27, 26,
24, 23,
22, 21
39,11
31, 20,
19, 18
14
36,
37
I/O, Type
I, LVDS
O, LVDS
I, LVCMOS
I, LVCMOS
I, LVCMOS
O, LVCMOS
35,
34,
33,
32
1, 2,
9, 10,
12, 13,
17, 40
38
I, LVCMOS
NC
I, LVCMOS
3, 8,
15,25, 30
16, DAP
Power
Power
SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013
PIN DESCRIPTIONS
Pin Description
Inverting and non-inverting high speed LVDS input pins.
Inverting and non-inverting high speed LVDS output pins.
Receive equalization level select pins.
Transmit pre-emphasis level select pins.
Input select pin.
Loss of Signal output pin, LOSn, reports when an open input fault condition is
detected at the input, INn. These are open drain outputs. External pull up
resistors are required.
Channel output power down pins. When the PWDNn is set to L, the channel
output, OUTn, is in the power down mode.
NO CONNECT pins. May be left floating.
Device power down pin. When the PWDN is set to L, the device is in the
power down mode.
Power supply pins.
Ground pin and a pad (DAP - die attach pad).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2007–2013, Texas Instruments Incorporated
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