DRV8818_16 Datasheet, PDF (3/31 Pages) Texas Instruments – Stepper Motor Controller IC

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5 Pin Configuration and Functions
DRV8818
SLVSAX9E – SEPTEMBER 2011 – REVISED JANUARY 2016
PWP Package
28-Pin HTSSOP
Top View
ISENA 1
HOME 2
DIR 3
AOUT1 4
DECAY 5
RCA 6
GND 7
VREF 8
RCB 9
VCC 10
BOUT1 11
USM1 12
USM0 13
ISENB 14
GND
(PPAD)
28 VMA
27 SLEEPn
26 ENABLEn
25 AOUT2
24 CP2
23 CP1
22 VCP
21 GND
20 VGD
19 STEP
18 BOUT2
17 RESETn
16 SRn
15 VMB
Pin Functions
PIN
NAME
NO.
TYPE ⁽¹⁾
DESCRIPTION
POWER AND GROUND
CP1
23
IO Charge pump flying capacitor
Connect a 0.22-μF capacitor between CP1 and CP2.
CP2
24
IO Charge pump flying capacitor
Connect a 0.22-μF capacitor between CP1 and CP2.
GND
7, 21
— Device ground
VCC
10
— Logic supply voltage
Connect to 3-V to 5-V logic supply. Bypass to GND with a 0.1-μF ceramic
capacitor.
VCP
VGD
22
IO High-side gate drive voltage
20
IO Low-side gate drive voltage
Connect a 0.22-μF ceramic capacitor to V_M.
Bypass to GND with a 0.22-μF ceramic capacitor.
VMA
VMB
28
— Bridge A power supply
15
— Bridge B power supply
Connect to motor supply (8 V to 35 V). Both VMA and VMB must be connected to
same supply.
CONTROL
DECAY
5
I
Decay mode select
Voltage applied sets decay mode - see motor driver description for details. Bypass
to GND with a 0.1-μF ceramic capacitor. Weak internal pulldown.
DIR
3
I
Direction input
Level sets the direction of stepping. Weak internal pulldown.
ENABLEn
26
I
Enable input
Logic high to disable device outputs, logic low to enable outputs. Weak internal
pullup to VCC.
ISENA
1
— Bridge A ground / Isense
Connect to current sense resistor for bridge A
ISENB
14
— Bridge B ground / Isense
Connect to current sense resistor for bridge B
RCA
6
I
Bridge A blanking and off time adjust Connect a parallel resistor and capacitor to GND - see motor driver description for
details.
RCB
9
I
Bridge B blanking and off time adjust Connect a parallel resistor and capacitor to GND - see motor driver description for
details.
RESETn
17
I
Reset input
Active-low reset input initializes the indexer logic and disables the H-bridge
outputs. Weak internal pullup to VCC.
SLEEPn
27
I
Sleep mode input
Logic high to enable device, logic low to enter low-power sleep mode. Weak
internal pulldown.
SRn
16
I
Sync. Rect. enable input
Active-low. When low, synchronous rectification is enabled. Weak internal
pulldown.
STEP
19
I
Step input
Rising edge causes the indexer to move one step. Weak internal pulldown.
USM0
13
I
Microstep mode 0
USM0 and USM1 set the step mode - full step, half step, quarter step, or eight
microsteps/step. Weak internal pulldown.
USM1
12
I
Microstep mode 1
USM0 and USM1 set the step mode - full step, half step, quarter step, or eight
microsteps/step. Weak internal pulldown.
VREF
8
I
Current set reference input
Reference voltage for winding current set
(1) Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output
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