DRV8804 Datasheet, PDF (3/15 Pages) Texas Instruments – QUAD SERIAL INTERFACE LOW-SIDE DRIVER IC

DRV8804
www.ti.com
SLVSAW4B – JULY 2011 – REVISED NOVEMBER 2011
Table 1. TERMINAL FUNCTIONS
NAME
PIN
(SOIC)
POWER AND GROUND
GND
5, 6, 7,
14, 15, 16
VM
1
CONTROL
nENBL
10
PIN
(HTSSOP)
5, 12,
PPAD
1
8
RESET
11
9
I/O ⁽¹⁾
-
-
I
I
DESCRIPTION
Device ground
Device power supply
Enable input
Reset input
LATCH
SDATIN
SDATOUT
SCLK
STATUS
nFAULT
OUTPUT
OUT1
OUT2
OUT3
OUT4
VCLAMP
13
11
I
Latch input
18
14
I
Serial data input
19
15
O Serial data output
17
13
I
Serial clock
20
16
OD Fault
3
3
O Output 1
4
4
O Output 2
8
6
O Output 3
9
7
O Output 4
2
2
-
Output clamp voltage
EXTERNAL COMPONENTS
OR CONNECTIONS
All pins must be connected to GND.
Connect to motor supply (8.2 V - 60 V).
Active low enables outputs – internal pulldown
Active-high reset input initializes internal
logic – internal pulldown
Rising edge latches shift register to output
stage – internal pulldown
Serial data input – internal pulldown
Serial data output – has weak internal
pullup – see serial interface section for details
Serial clock input – internal pulldown
Logic low when in fault condition (overtemp,
overcurrent)
Connect to load 1
Connect to load 2
Connect to load 3
Connect to load 4
Connect to VM supply, or zener diode to VM
supply
(1) Directions: I = input, O = output, OD = open-drain output
DW (WIDE SOIC) PACKAGE
(TOP SIDE)
VM 1
VCLAMP 2
OUT1 3
OUT2 4
GND 5
GND 6
GND 7
OUT3 8
OUT4 9
nENBL 10
20 _nFAULT
19 _SDATAO
18 _SDATAIN
17 _SCLK
16 _GND
15 _GND
14 _GND
13 _LATCH
12 _NC
11 _RESET
PWP (HTSSOP) PACKAGE
(TOP SIDE)
VM 1
VCLAMP 2
OUT1 3
OUT2 4
GND 5
OUT3 ⁶
OUT4 ⁷
nENBL ⁸
16 _nFAULT
15 _SDATAO
14 _SDATAIN
13 _SCLK
GND
12 _GND
11 _LATCH
10 _NC
9 _RESET
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): DRV8804
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