CDCLVC11XX_12 Datasheet, PDF (3/23 Pages) Texas Instruments – 3.3 V and 2.5 V LVCMOS High-Performance Clock Buffer Family

CDCLVC11xx
www.ti.com
SCAS895 – MAY 2010
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
VALUE / UNIT
V_DD
Supply voltage range
V_IN
Input voltage range ⁽²⁾
V_O
Output voltage range ⁽²⁾
I_IN
Input current
I_O
Continuous output current
T_J
Maximum junction temperature
T_ST
Storage temperature range
–0.5 V to 4.6 V
–0.5 V to V_DD + 0.5 V
–0.5 V to V_DD + 0.5 V
±20 mA
±50 mA
125°C
–65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 4.6 V maximum.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
q_JA
q_JC(top)
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance ⁽³⁾
DCDLVC1102/03/04
PW
8 PINS
149.4
69.4
CDCLVC1106
PW
14 PINS
112.6
48.0
CDCLVC1108
PW
16 PINS
108.4
33.6
CDCLVC11010
PW
20 PINS
83.0
32.3
CDCLVC1112
PW
24 PINS
87.9
26.5
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
V_DD
Supply voltage range
3.3 V supply
2.5 V supply
V_IL
Low-level input voltage
V_DD = 3.0 V to 3.6 V
V_DD = 2.3 V to 2.7 V
V_IH
High-level input voltage
V_DD = 3.0 V to 3.6 V
V_DD = 2.3 V to 2.7 V
V_th
Input threshold voltage
V_DD = 2.3 V to 3.6 V
t_r / t_f
Input slew rate
t_w
Minimum pulse width at
CLKIN
V_DD = 3.0 V to 3.6 V
V_DD = 2.3 V to 2.7 V
f_CLK
LVCMOS clock Input
Frequency
V_DD = 3.0 V to 3.6 V
V_DD = 2.3 V to 2.7 V
T_A
Operating free-air temperature
MIN
3.0
2.3
V_DD/2 + 600
V_DD/2 + 400
1
1.8
2.75
DC
DC
–40
NOM
3.3
2.5
MAX
3.6
2.7
V_DD/2 – 600
V_DD/2 – 400
V_DD/2
4
250
180
85
UNIT
V
mV
mV
mV
V/ns
ns
MHz
°C
Copyright © 2010, Texas Instruments Incorporated
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