CD74FCT573_16 Datasheet, PDF (3/12 Pages) Texas Instruments – BiCMOS OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

CD74FCT573, CD74FCT573AT
BiCMOS OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS744A – JULY 2000 – REVISED JULY 2000
recommended operating conditions (see Note 2)
MIN MAX UNIT
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
4.75 5.25 V
2
V
0.8 V
0 VCC V
0 VCC V
–15 mA
48 mA
0
10 ns/V
TA
Operating free-air temperature
0
70 °C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
MIN MAX
VIK
VOH
VOL
II
IOZ
IOS†
ICC
∆ICC‡
II = –18 mA
IOH = –15 mA
IOL = 48 mA
VI = VCC or GND
VO = VCC or GND
VI = VCC or GND,
VI = VCC or GND,
One input at 3.4 V,
Other inputs at VCC or GND
VO = 0
IO = 0
4.75 V
4.75 V
4.75 V
5.25 V
5.25 V
5.25 V
5.25 V
5.25 V
–1.2
2.4
2.4
0.55
±0.1
±0.5
–60
–60
8
1.6
Ci
VI = VCC or GND
10
Co
VO = VCC or GND
15
† _{Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms.}
‡ _{This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.}
MAX
–1.2
0.55
±1
±10
80
1.6
10
15
UNIT
V
V
V
mA
mA
mA
mA
mA
pF
pF
timing requirements over recommended operating temperature conditions (unless otherwise
noted) (see Figure 1)
tw Pulse duration
tsu Setup time
th
Hold time
LE high
Data before LE↓
Data after LE↓
CD74FCT573
MIN MAX
6
2
1.5
CD74FCT573AT
MIN MAX
5
2
1.5
UNIT
ns
ns
ns
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