BQ2031PN-A5 Datasheet, PDF (3/19 Pages) Texas Instruments – Lead-Acid Fast-Charge IC

bq2031
n Fast charge termination
n Maintenance charging
n Charge regulation
Charge Algorithms
Three charge algorithms are available in the bq2031:
n Two-Step Voltage
n Two-Step Current
n Pulsed Current
The state transitions for these algorithms are described
in Table 1 and are shown graphically in Figures 2
through 4. The user selects a charge algorithm by con-
figuring pins QSEL and TSEL.
Charge Qualification
The bq2031 starts a charge cycle when power is applied
while a battery is present or when a battery is inserted.
Figure 1 shows the state diagram for pre-charge qualifi-
cation and temperature monitoring. The bq2031 first
checks that the battery temperature is within the al-
lowed, user-configurable range. If the temperature is
out-of-range (or the thermistor is missing), the bq2031
enters the Charge Pending state and waits until the bat-
tery temperature is within the allowed range. Charge
Pending is annunciated by LED3 flashing.
Chip On
VCC 4.5V
Temperature
Checks On
Present
VLCO < VCELL < VHCO
Test 1
Temperature
in Range
Battery
Status?
ISNS < ICOND
Voltage
Regulation
@ VFLT +
0.25V
Fail:
t = tQT1 or
VCELL > VHCO
PASS: ISNS > ICOND
Temperature Out
of Range or
Thermistor Absent
Absent
VCELL < VLCO or
VCELL > VHCO
Fault
LED3 = 1
MOD = 0
VCELL
VCELL
VLCO or
VHCO
Test 2
VCELL < VMIN
Current
Regulation
@ICOND
Fail:
t = tQT2 or
VCELL < VLCO or
VCELL > VHCO
PASS: VCELL > VMIN
Bulk
Charge
VCELL < VLCO or
VCELL > VHCO
Termination
VCELL < VMIN
Charge
Pending
LED3 Flash
MOD = 0
Temperature Out
of Range or
Thermistor Absent
Fast
Charge
Temperature In
Range, Return
to Original State
FG203101.eps
Figure 1. Cycle Start/Battery
Qualification State Diagram
Table 1. bq2031 Charging Algorithms
Algorithm/State
Two-Step Voltage
Fast charge, phase 1
Fast charge, phase 2
Primary termination
Maintenance
Two-Step Current
Fast charge
Primary termination
Maintenance
Pulsed Current
Fast charge
Primary termination
Maintenance
QSEL
L
H
H
TSEL
H/L^{Note 1}
L
H
Conditions
-
while VBAT < VBLK, ISNS = IMAX
while ISNS > IMIN, VBAT = VBLK
ISNS = IMIN
VBAT = VFLT
-
while VBAT < VBLK, ISNS = IMAX
VBAT = VBLK or ∆²V < -8mV^{Note 2}
ISNS pulsed to average IFLT
-
while VBAT < VBLK, ISNS = IMAX
VBAT = VBLK
ISNS = IMAX after VBAT = VFLT;
ISNS = 0 after VBAT = VBLK
MOD Output
-
Current regulation
Voltage regulation
Voltage regulation
-
Current regulation
Fixed pulse current
-
Current regulation
Hysteretic pulsed
current
Notes:
1. May be high or low, but do not float.
2. A Unitrode proprietary algorithm for accumulating successive differences between samples of VBAT.
3