ADC12DC105_14 Datasheet, PDF (3/24 Pages) Texas Instruments – Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

www.ti.com
Pin No.
ANALOG I/O
3
13
Symbol
V_INA+
V_INB+
2
V_INA-
14
V_INB-
5
V_RPA
11
V_RPB
7
V_CMOA
9
V_CMOB
6
V_RNA
10
V_RNB
59
V_REF
DIGITAL I/O
19
OF/DCS
18
CLK
ADC12DC105
SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008
PIN DESCRIPTIONS
Equivalent Circuit
Description
V_A
Differential analog input pins. The differential full-scale input signal
level is 2V_P-P with each input pin signal centered on a common mode
voltage, V_CM.
AGND
(1)
V_A
V_A
V_A
V_A
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close to
the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor
should be placed between V_RP and V_RN as close to the pins as
possible, and a 1 µF capacitor should be placed in parallel.
V_RP and V_RN should not be loaded. V_CMO may be loaded to 1mA for
use as a temperature stable 1.5V reference.
It is recommended to use V_CMO to provide the common mode
voltage, V_CM, for the differential analog inputs.
AGND
V_A
AGND
AGND
(2)
Reference Voltage. This device provides an internally developed
1.2V reference. When using the internal reference, V_REF should be
decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series
inductance (ESL) capacitor.
This pin may be driven with an external 1.2V reference voltage.
This pin should not be used to source or sink current when the
internal reference is used.
(3)
VA
This is a four-state pin controlling the input clock mode and output
data format.
OF/DCS = V_A, output data format is 2's complement without duty
cycle stabilization applied to the input clock.
OF/DCS = AGND, output data format is offset binary, without duty
cycle stabilization applied to the input clock.
OF/DCS = (2/3)*V_A, output data is 2's complement with duty cycle
stabilization applied to the input clock.
AGND
(4)
OF/DCS = (1/3)*V_A, output data is offset binary with duty cycle
stabilization applied to the input clock.
The clock input pin.
VA
The analog inputs are sampled on the rising edge of the clock input.
57
PD_A
20
PD_B
Copyright © 2008, Texas Instruments Incorporated
This is a two-state input controlling Power Down.
PD = V_A, Power Down is enabled and power dissipation is reduced.
PD = AGND, Normal operation.
AGND
(5)
Product Folder Links: ADC12DC105
Submit Documentation Feedback
3