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AM5706_17 Datasheet, PDF (297/386 Pages) Texas Instruments – Sitara Processors
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AM5706, AM5708
SPRS961A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-171. PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
NO.
1
PARAMETER
td(TX_CLK-TXD)
td(TX_CLK-TX_EN)
td(TX_CLK-TXD)
td(TX_CLK-TX_EN)
DESCRIPTION
Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN valid
Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN valid
SPEED
10 Mbps
100 Mbps
MIN MAX UNIT
5
25 ns
5
25 ns
1
MII_TXCLK (input)
MII_TXD[3:0],
MII_TXEN (outputs)
Figure 5-123. PRU-ICSS MII_TXD[3:0], MII_TXEN Timing
SPRS91x_TIMING_PRU_MII_RT_07
5.9.6.22.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
Table 5-172. Timing Requirements for PRU-ICSS UART Receive
NO. PARAMETER
DESCRIPTION
3
tw(RX)
Pulse duration, receive start, stop, data bit
(1) U = UART baud time = 1/programmed baud rate.
MIN
0.96U (1)
MAX UNIT
1.05U ns
Table 5-173. Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART
Transmit
NO. PARAMETER
DESCRIPTION
1
ƒbaud(baud)
Maximum programmable baud rate
2
tw(TX)
Pulse duration, transmit start, stop, data bit
(1) U = UART baud time = 1/programmed baud rate.
MIN
0
U - 2 (1)
MAX
12
U+2
UNIT
MHz
ns
2
1
UART_TXD
Start
Bit
Data Bits
3
4
UART_RXD
Start
Bit
Data Bits
SPRS961_TIMING_UART_01
Figure 5-124. PRU-ICSS UART Timing
5.9.6.22.5 PRU-ICSS IOSETs
In Table 5-174 are presented the specific groupings of signals (IOSET) for use with PRU-ICSS1.
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