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| TPS65094 Datasheet, PDF (29/92 Pages) Texas Instruments – PMIC for Intel Apollo Lake Platform | |||
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www.ti.com
TPS65094, TPS650940, TPS650941, TPS650942, TPS650944
SWCS133A â SEPTEMBER 2015 â REVISED JUNE 2016
6.2 Functional Block Diagram
Figure 6-1 shows a functional block diagram of the PMIC.
Optional(a)
Required(b)
LDO5V
EC
SoC
V1P8A
V1P8A
PMICEN
SLP_S3B
SLP_S4B
SLP_S0B
LDOLS_EN(a)
SWA1_EN(b)
THERMTRIPB
Control
Inputs
CLK
DATA
I2C CTRL
IRQB
Control
Outputs
PCH_PWROK
Internal
RSMRSTB Interrupt
PROCHOT
Events
GPO
VSYS
BUCK5V
LDO5V
VSYS
V5ANA
LDO5
LDO3P3
VREF
REFSYS
nPUC
AGND
LDOA1
1.35 V to 3.3 V
1.8 V(b)
200 mA
EN
TEST CTRL
OTP
REGISTERS
Digital Core
Thermal
monitoring
Thermal shutdown
VSET
EN
BUCK1
Default: 1V
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
5A
BOOT1
DRVH1
SW1
DRVL1
FBVOUT1
PGNDSNS1
ILIM1
VSYS
VSET
EN
BUCK2
Default: 0V
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
21 A
BOOT2
DRVH2
SW2
DRVL2
FBVOUT2
PGNDSNS2
FBGND2
ILIM2
VSET
EN
PVIN3
BUCK3
LX3
Default: 1.05 V
3A
FB3
<PGND_BUCK3>
VSET
EN
PVIN4
BUCK4
LX4
Default: 1.8 V
2A
FB4
<PGND_BUCK4>
VSET
EN
PVIN5
BUCK5
LX5
Default: 1.24 V
2A
FB5
<PGND_BUCK5>
VSET
EN
BUCK6
Default: OTP
Dependent
7A
BOOT6
DRVH6
SW6
DRVL6
FBVOUT6
PGNDSNS6
ILIM6
VSYS
BUCK5V
BUCK5V
BUCK5V
VSYS
EN
VTT_LDO
½ à VDDQ
ILIM set by OTP
PVINVTT
VTT
VTTFB
VNN
VCCGI
VCCRAM
V1P8A
V1P24A
VDDQ
VTT
LDOA2
0.7 V to 1.5 V
600 mA
LDOA3
0.7 V to 1.5 V
600 mA
LOAD SWA1
300 mA
LOAD SWB1
400 mA
LOAD SWB2
400 mA
Dashed connections optional.
Refer to Pin Attributes for
connection if unused.
(1) LPDDR3 and LPDDR4
(2) DDR3L
(a) LDOA1 1RW ³$OZD\V 2Q´
(b) LDOA1 ³$OZD\V 2Q´
0.5 V to 3.3 V
V1P8A(1)
0.5 V to 3.3 V(2)
Figure 6-1. PMIC Functional Block Diagram
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2015â2016, Texas Instruments Incorporated
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