TPS62366A Datasheet, PDF (29/48 Pages) Texas Instruments – 4A Processor Supply with I2C Compatible Interface and Remote Sense

TPS62366A, TPS62366B
www.ti.com
SLUSAX3 – JULY 2012
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 44). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 45) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
SDA
SCL
Data line stable;
data valid
Change of
data allowed
Figure 44. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 43). This releases the bus and stops the communication link with the
addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section results in 00h being read out.
Data Output
by Transmitter
Data Output
by Receiver
Not Acknowledge
Acknowledge
SCL
S
START condition
1
2
8
Figure 45. Acknowledge on the I²C Bus
9
Clock Pulse for
Acknowledgment
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