CC1020_17 Datasheet, PDF (29/95 Pages) Texas Instruments – Low-Power RF Transceiver for Narrowband Systems

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CC1020
SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015
5.9.3 Demodulator, Bit Synchronizer, and Data Decision
The block diagram for the demodulator, data slicer and bit synchronizer is shown in Figure 5-10. The built-
in bit synchronizer synchronizes the internal clock to the incoming data and performs data decoding. The
data decision is done using over-sampling and digital filtering of the incoming signal. This improves the
reliability of the data transmission. Using the synchronous modes simplifies the data-decoding task
substantially.
The recommended preamble is a ‘010101…’ bit pattern. The same bit pattern should also be used in
Manchester mode, giving a ‘011001100110…‘chip’ pattern. This is necessary for the bit synchronizer to
synchronize to the coding correctly.
The data slicer does the bit decision. Ideally the two received FSK frequencies are placed symmetrically
around the IF frequency. However, if there is some frequency error between the transmitter and the
receiver, the bit decision level should be adjusted accordingly. In CC1020, this is done automatically by
measuring the two frequencies and use the average value as the decision level.
The digital data slicer in CC1020 uses an average value of the minimum and maximum frequency
deviation detected as the comparison level. The RXDEV_X[1:0] and RXDEV_M[3:0] in the
AFC_CONTROL register are used to set the expected deviation of the incoming signal. Once a shift in the
received frequency larger than the expected deviation is detected, a bit transition is recorded and the
average value to be used by the data slicer is calculated.
The minimum number of transitions required to calculate a slicing level is 3. That is, a 010 bit pattern
(NRZ).
The actual number of bits used for the averaging can be increased for better data decision accuracy. This
is controlled by the SETTLING[1:0] bits in the AFC_CONTROL register. If RX data is present in the
channel when the RX chain is turned on, then the data slicing estimate will usually give correct results
after 3 bit transitions. The data slicing accuracy will increase after this, depending on the SETTLING[1:0]
bits. If the start of transmission occurs after the RX chain has turned on, the minimum number of bit
transitions (or preamble bits) before correct data slicing will depend on the SETTLING[1:0] bits.
The automatic data slicer average value function can be disabled by setting SETTLING[1:0] = 00. In this
case a symmetrical signal around the IF frequency is assumed.
The internally calculated average FSK frequency value gives a measure for the frequency offset of the
receiver compared to the transmitter. This information can also be used for an automatic frequency control
(AFC) as described in Section 5.9.13.
Average filter
Digital filtering
Frequency
detector
Decimator
Data
filter
Figure 5-10. Demodulator Block Diagram
Data slicer
comparator
Bit synchronizer
and data decoder
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