ADS7945_14 Datasheet, PDF (29/50 Pages) Texas Instruments – 14-Bit, 2 MSPS, Dual-Channel, Differential/Single-Ended, Ultralow-Power Analog-to-Digital Converters

ADS7945
ADS7946
www.ti.com
DEVICE OPERATION
SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
The ADS7945/6 operate with either a 16-clock frame or 32-clock frame for ease of interfacing with the host
processor.
16-CLOCK FRAME
Figure 81 shows the devices operating in 16-clock mode. This mode is the fastest mode for device operation. In
this mode, the devices output data from previous conversions while converting the recently sampled signal.
As shown in Figure 81, the ADS7945/6 start acquisition of the analog input from the 16th falling edge of SCLK.
The device samples the input signal on the CS falling edge. SDO comes out of 3-state and the device outputs
the MSB on the CS falling edge. The device outputs the next lower SDO bits on every SCLK falling edge after it
has first seen the SCLK rising edge. The data correspond to the sample and conversion completed in the
previous frame. During a CS low period, the device converts the recently sampled signal. It uses SCLK for
conversions. Conversion is complete on the 16th SCLK falling edge. CS can be high at any time after the 16th
SCLK falling edge (see the Parameter Measurement Information for more details). The CS rising edge after the
16th SCLK falling edge and before the 29th SCLK falling edge keeps the device in the 16-clock data frame. The
device output goes to 3-state when CS is high. It is also permissible to stop SCLK after the device has seen the
16th SCLK falling edge.
Sample N
Sample N + 1
t_CONV
t_ACQ
CS
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SDO
D13 D12 D11 D10 D9 D8 D7 D6 D4 D3 D3 D2 D1 D0
Data From Sample N - 1
Figure 81. ADS7945/6 Operating in 16-Clock Mode without Power-Down (PDEN = 0)
32-CLOCK FRAME
Figure 82 shows the devices operating in 32-clock mode. In this mode, the devices convert and output the data
from the most recent sample before taking the next sample.
Sample N
CS
t_CONV
1/f_SAMPLE
t_ACQ
Sample N + 1
SCLK
12
11 12 16 17 18 23 24 25 26 27 28 29 30 31 32
SDO
D13 D12 D7 D6 D5 D4 D3 D2 D1 D0
Data From Sample N
Figure 82. ADS7945/6 Operation in 32-Clock Frame without Power-Down (PDEN = 0)
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ADS7945 ADS7946
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