TMS570LS20206-EP_16 Datasheet, PDF (28/107 Pages) Texas Instruments – Series 16/32-BIT RISC Flash Microcontroller

TMS570LS20206-EP, TMS570LS20216-EP
SPNS209A – JUNE 2012 – REVISED AUGUST 2012
www.ti.com
Name
PORRST
RST
ECLK
TCK
RTCK
TDI
TDO
TMS
TRST
TEST
ERROR
FLTP1
FLTP2
V_CCP
Table 2-9. Terminal Functions (continued)
Terminal
TMS570LS20216
337
144
W7
28
B17
85
A12
88
B18
30
A16
35
A17
34
C18
33
C19
36
D18
29
U2
58
B14
143
J5
122
H5
123
F8
128
TMS570LS20206
337
144
Type
Internal
pullup/p
ulldown
Description
System Module (SYS)
W7
28
3.3V I
IPD
(100µA)
Power on Reset Pin. External power
supply monitor circuitry must assert a
power-on reset on this pin.
Active Low Bidirectional Reset pin. An
external device can assert a device reset
on this pin.
The output buffer on this pin is
B17
85
4mA
IPU implemented as an open drain (drives
(100µA) low only).
3.3V I/O
To ensure an external reset is not
arbitrarily generated, TI recommends
that an external pullup resistor is
connected to this pin.
A12
88
8mA
IPD External Clock Prescaler module output
(20µA) pin or GIO pin
Tset/Debug (T/D)
B18
30
3.3V I
IPD JTAG test clock pin. Clocks the JTAG
(100uA) debug logic.
A16
35
3.3V O
JTAG return test clock pin. (JTAG)
A17
34
IPU
(100uA)
JTAG test data in pin.
C18
33
3.3V I/O
8 mA
IPD
(100uA)
JTAG test data out pin.
C19
36
IPU
(100uA)
JTAG serial input pin for controlling the
state of the CPU test access port (TAP)
controller.
D18
29
3.3V I
U2
58
IPD
(100uA)
IPD
(100uA)
JTAG test hardware reset to TAP. IEEE
Standard 1149-1 (JTAG) Boundary-Scan
Logic
Test enable pin. Reserved for internal TI
use only. For proper operation, this pin
must be connected to ground, e.g. using
a external resistor.
Error Signaling Module (ESM)
B14
143
3.3V I/O 8mA
IPD
(20uA)
Error Signaling pin
Flash
J5
122
Flash Test Pad 1 pin. For proper
operation this pin must connect only to a
test pad or not be connected at all [no
connect (NC)]. The test pad must not be
exposed in the final product where it
might be subjected to an ESD event.
H5
123
Flash Test Pad 2 pin. For proper
operation this pin must connect only to a
test pad or not be connected at all [no
connect (NC)]. The test pad must not be
exposed in the final product where it
might be subjected to an ESD event.
F8
128
3.3V
PWR
Flash pump voltage supply (3.3 V). This
pin is required for Flash read, program
and erase operations.
28
Device Overview
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS570LS20206-EP TMS570LS20216-EP