TLV320AIC3110_14 Datasheet, PDF (28/127 Pages) Texas Instruments – Low-Power Audio Codec With Audio Procsessing and Stereo Class-D Speaker Amplifier

TLV320AIC3110
SLAS647 – DECEMBER 2009
www.ti.com
ADC power up is controlled by writing to page 0 / register 81, bit D7. An ADC power-up condition can be
verified by reading page 0 / register 36, bit D6.
5.4.4 ADC Decimation Filtering and Signal Processing
The TLV320AIC3110 ADC channel includes built-in digital decimation filters to process the oversampled
data from the delta-sigma modulator to generate digital data at the Nyquist sampling rate with high
dynamic range. The decimation filter can be chosen from three different types, depending on the required
frequency response, group delay, and sampling rate.
5.4.4.1 ADC Processing Blocks
The TLV320AIC3110 offers a range of processing blocks which implement various signal processing
capabilities along with decimation filtering. These processing blocks give users the choice of how much
and what type of signal processing they may use and which decimation filter is applied.
The choices among these processing blocks allow the system designer to balance power conservation
and signal-processing flexibility. Less signal-processing capability reduces the power consumed by the
device. Table 5-16 gives an overview of the available processing blocks of the ADC channel and their
properties. The resource-class (RC) column gives an approximate indication of power consumption.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• Variable-tap FIR filter
• AGC
The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group
delay in combination with various signal-processing effects such as audio effects and frequency shaping.
The available first-order IIR, biquad, and FIR filters have fully user-programmable coefficients.
Processing
Blocks
PRB_R4
PRB_R5
PRB_R6
PRB_R10
PRB_R11
PRB_R12
PRB_R16
PRB_R17
PRB_R18
Channel
Mono
Mono
Mono
Mono
Mono
Mono
Mono
Mono
Mono
Table 5-16. ADC Processing Blocks
Decimation
Filter
A
A
A
B
B
B
C
C
C
First-Order
IIR Available
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Number of
Biquads
0
5
0
0
3
0
0
5
0
FIR
No
No
25-tap
No
No
20-tap
No
No
25-tap
Required
AOSR Value
128, 64
128, 64
128, 64
64
64
64
32
32
32
Resource
Class
3
4
4
2
2
2
2
2
2
28
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