ADS7863_14 Datasheet, PDF (28/44 Pages) Texas Instruments – Dual, 2MSPS, 12-Bit, 2 + 2 or 3 + 3 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER

ADS7863
SBAS383E – JUNE 2007 – REVISED JANUARY 2011
Power-Down Modes and Reset
(Not ADS7861-Compatible)
The ADS7863 has a comprehensive built-in
power-down feature. There are three power-down
modes: deep power-down, nap power-down, and
auto-nap power-down. All three power-down modes
are activated with the 12th falling CLOCK edge of the
SDI access, during which the related bit asserts (DP
= '1', N = '1', or AN = '1'). All modes are deactivated
by de-asserting the respective bit in the SDI Register.
Contents of the SDI Register are not affected by any
of the power-down modes. Any ongoing conversion
aborts when deep or nap power-down is initiated.
Table 10 lists the differences among the three
power-down modes.
In deep power-down mode, all functional blocks
except the digital interface are disabled. The analog
block has its bias currents turned off. In this mode,
the power dissipation reduces to 1mA within 2ms. The
wake-up time from deep power-down mode is 1ms.
In nap power-down mode, the ADS7863 turns off
the biasing of the comparator and the mid-voltage
buffer within 200ns. The device goes into nap
power-down mode regardless of the conversion state.
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The auto-nap power-down mode is very similar to
the nap mode. The only differences are the methods
of powering down and waking up the device. The SDI
Register bit AN is only used to enable/disable this
feature. If the auto-nap mode is enabled, the
ADS7863 turns off the biasing automatically after
finishing a conversion; thus, the end of conversion
actually activates the auto-nap power-down. The
device powers down within 200ns in this mode, as
well. Triggering a new conversion by applying a
CONVST pulse puts the device back into normal
operation and automatically starts a new conversion
six CLOCK cycles later. Therefore, a complete
conversion cycle takes 19 CLOCK cycles; thus, the
maximum throughput rate in auto-nap power-down
mode is reduced to 1.68MSPS.
To issue a device reset, an RD pulse must be
generated along with an SDI word containing A[2:0] =
'101'. With the 12th falling edge after generating the
RD pulse, the entire device—including the serial
interface—is forced into reset. After approximately
500ns, the serial interface becomes active again.
POWER-DOWN
TYPE
Deep
Nap
Auto-nap
ENABLED
BY
DP = ‘1’
N = ‘1’
AN = ‘1’
Table 10. Power-Down Modes
ACTIVATED BY
13th clock
13th clock
Each end of
conversion
ACTIVATION
TIME
2ms
200ns
200ns
RESUMED
BY
DP = ‘0’
N = ‘0’
CONVST pulse
REACTIVATION TIME
1ms
3 clocks
3 clocks
DISABLED
BY
DP = ‘0’
N = ‘0’
AN = ‘0’
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