LM3S2B93_16 Datasheet, PDF (278/1196 Pages) Texas Instruments – Stellaris LM3S2B93 Microcontroller

System Control
Register 33: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
reserved EPI0 reserved I2S0 reserved COMP2 COMP1 COMP0
Type RO
R/W
RO
R/W
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
15
reserved
Type RO
Reset
0
14
I2C1
R/W
0
13
reserved
RO
0
12
I2C0
R/W
0
11
10
reserved
RO
RO
0
0
9
QEI1
R/W
0
8
QEI0
R/W
0
23
22
21
reserved
RO
RO
RO
0
0
0
7
6
reserved
RO
RO
0
0
5
SSI1
R/W
0
20
19
18
17
16
TIMER3 TIMER2 TIMER1 TIMER0
RO
R/W
R/W
R/W
R/W
0
0
0
0
0
4
SSI0
R/W
0
3
2
1
0
reserved UART2 UART1 UART0
RO
R/W
R/W
R/W
0
0
0
0
Bit/Field
31
30
29
28
27
Name
reserved
EPI0
reserved
I2S0
reserved
Type
RO
R/W
RO
R/W
RO
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
EPI0 Clock Gating
This bit controls the clock gating for EPI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2S0 Clock Gating
This bit controls the clock gating for I2S module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
278
July 03, 2014
Texas Instruments-Production Data