TVP7002_16 Datasheet, PDF (27/58 Pages) Texas Instruments – TRIPLE 8-/10-BIT 165-/110-MSPS VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL

TVP7002
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Register Definitions
Chip Revision
Subaddress 00h
7
6
5
Chip revision [7:0]: Chip revision number
4
3
Chip revision [7:0]
SLES206C – MAY 2007 – REVISED APRIL 2013
Read Only
2
1
0
H-PLL Feedback Divider MSBs
Subaddress 01h
Default (67h)
7
6
5
4
3
2
1
0
PLL divide [11:4]
PLL divide [11:0]: Controls the 12-bit horizontal PLL feedback divider value that determines the number of pixels per line. PLL divide [11:4]
bits should be loaded first whenever a change is required.
H-PLL Feedback Divider LSBs
Subaddress 02h
Default (20h)
7
6
5
4
3
2
1
0
PLL divide [3:0]
Reserved
PLL divide [11:0]: Controls the 12-bit horizontal PLL feedback divider value that determines the number of pixels per line. PLL divide [11:4]
bits should be loaded first whenever a change is required.
H-PLL Control
Subaddress 03h
7
6
VCO [1:0]
5
4
3
Charge Pump Current [2:0]
Default (A8h)
2
1
0
Reserved
VCO [1:0]: Selects VCO frequency range
00 =
VCO Gain
(K_VCO)
75
VCO Range
Ultra low
Pixel Clock Frequency (PCLK)
PCLK < 36 MHz
01 =
85
Low
36 MHz ≤ PCLK < 70 MHz
10 =
150
Medium (default)
70 MHz ≤ PCLK < 135 MHz
11 =
200
High
135 MHz ≤ PCLK ≤ 165 MHz
Charge Pump Current [2:0]: Selects PLL charge pump current setting. The recommended charge pump current setting (ICP) can be
determined using the following equation.
I_CP = 40 × K_VCO/(pixels per line)
000 = 0: Small
101 = 5 (default)
111 = 7: Large
NOTE: Also see the PLL and CLAMP Control register at subaddress 0Fh.
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