TSC2008-Q1 Datasheet, PDF (27/39 Pages) Texas Instruments – 1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire Micro TOUCH SCREEN CONTROLLER with SPI™

TSC2008-Q1
www.ti.com
SBAS552 – JUNE 2011
POWER DISSIPATION
There are two major power modes for the TSC2008-Q1: full-power (PD0 = '1') and auto power-down (PD0 = '0').
Unlike its predecessor, the TSC2046/2046E (where operation is synchronous to SCLK and therefore power
depends on the SCLK frequency), the TSC2008-Q1 uses an internal clock for conversion and is asynchronous to
SCLK. TSC2008-Q1 power consumption depends on the sample rate and is minimally affected by the SCLK
frequency. Figure 31 shows a timing example using 12-bit resolution and 24 SCLKs per cycle. There are
approximately 2.5 SCLKs of acquisition time used at the end of the 8-bit command cycle. When the
preprocessing filter is on, the next six acquisition cycles are controlled by the internal conversion clock instead of
relying on the external SCLK. A conversion time follows each acquisition time. Because there are six more
conversions to be completed, and also because of the power used from preprocessing, the power consumption
when the filter is on is higher than the power consumed without the filter at the same output rate, as shown in
Figure 35. This timing sequence also applies to Figure 32 to Figure 34. Thus, using the TSC2008-Q1, power
consumption can be very low, even with a low SCLK frequency.
400
12-Bit AUX Conversion with MAV
350 _{SCLK = 16MHz}
VDD = 1.8V
300 _{TA = +25°C}
250
200
150
100
50
0
0
2
4
6
8
10
12
14
Sample Output Rate (kHz)
400
12-Bit AUX Conversion without MAV
350 _{SCLK = 16MHz}
VDD = 1.8V
300 _{TA = +25°C}
250
200
150
100
50
0
0 10 20 30 40 50 60 70 80 90
Sample Output Rate (kHz)
Figure 35. Sample Output Rate vs Supply Current (with and without MAV filter)
Another important consideration for power dissipation is the reference mode of the converter. In the single-ended
reference mode, the touch panel drivers are on only when the analog input voltage is being acquired (see
Figure 31 and Table 4). The external device (for example, a resistive touch screen), therefore, is only powered
during the acquisition period. In the differential reference mode, the external device must be powered throughout
the acquisition and conversion periods (see Figure 31). If the conversion rate is high, using this mode could
substantially increase power dissipation.
THROUGHPUT RATE AND SPI BUS TRAFFIC
Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus is
much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The
throughput is further limited by the SPI bus bandwidth, which is determined by the supply voltage and what the
host processor can support. The effective throughput is approximately 20kSPS at 8-bit resolution, or 10kSPS at
12-bit resolution. The preprocessing saves a large portion of the SPI bandwidth for the system to use on other
devices.
Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). The TSC2008-Q1
contains an internal clock that drives the state machines that perform the many functions of the device. This
clock is divided down to provide a clock that runs the A/D converter. The 8-bit ADC mode uses a 4MHz clock
and the 12-bit ADC mode uses a 2MHz clock. The actual frequency of this internal clock is slower than the name
suggests, and varies with the supply voltage. For a typical internal 4MHz OSC clock, the frequency actually
ranges from 3.66MHz to 3.82MHz. For VDD = 1.2V, the frequency reduces to 3.19MHz, which gives a
3.19MHz/16 = 199kSPS raw A/D converter sample rate.
Copyright © 2011, Texas Instruments Incorporated
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