TPS62650-Q1 Datasheet, PDF (27/40 Pages) Texas Instruments – 800-mA, 6-MHz High-Efficiency Step-Down Converter With I2C™ Compatible Interface in Chip-Scale Packaging

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Recognize START or
REPEATED START
Condition
SDA
MSB
Address
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
TPS62650-Q1
SLVSB62A – MARCH 2012 – REVISED MARCH 2012
Recognize STOP or
REPEATED START
Condition
P
Sr
R/W
SCL
S
or
Sr
1
2
START or
Repeated START
Condition
7
8
9
ACK
1
2
Clock Line Held Low While
Interrupts are Serviced
Figure 53. Bus Protocol
3−8
9
Sr
ACK
or
P
STOP or
Repeated START
Condition
TPS62650-Q1 I²C Update Sequence
The TPS62650-Q1 requires a start condition, a valid I²C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS62650-Q1 device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. A valid I²C address selects the TPS62650-Q1. TPS62650-Q1
performs an update on the falling edge of the LSB byte.
When the TPS62650-Q1 is in hardware shutdown (EN pin tied to ground) the device can not be updated via the
I²C interface. Conversely, the I²C interface is fully functional during software shutdown (EN_DCDC bit = 0).
1
7
1
1
8
1
S
Slave Address
R/W A
Register Address
A
8
Data
1
1
A
P
“0” Write
From Master to TPS6265x
From TPS6265x to Master
A = Acknowledge
S = START condition
P = STOP condition
Figure 54. "Write" Data Transfer Format in Standard, Fast- and Fast-Plus Modes
1
7
1
1
8
1
1
7
1
1
S
Slave Address
R/W A
Register Address
A Sr
Slave Address
R/W A
8
Data
1
1
A
P
“0” Write
From Master to TPS6265x
From TPS6265x to Master
“1” Read
A = Acknowledge
A = Not Acknowledge
S = START condition
Sr = REPEATED START condition
P = STOP condition
Figure 55. "Read" Data Transfer Format in Standard, Fast- and Fast-Plus Modes
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62650-Q1
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