TPS54060-Q1 Datasheet, PDF (27/52 Pages) Texas Instruments – 0.5-A 60-V STEP-DOWN SWIFT™ DC/DC CONVERTER WITH Eco-mode™

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COMP
c
R3
C2
C1
TPS54060-Q1
SLVSA25A – JANUARY 2010 – REVISED MARCH 2011
DETAILED DESCRIPTION (continued)
Power Stage
gm_ps 1.9 A/V
PH
V_O
a
b
R1
R_ESR
R_L
CO RO
0.8 V
gm_ea
97 mA/V
VSENSE
R2
C_OUT
Figure 47. Small Signal Model for Loop Response
Simple Small Signal Model for Peak Current Mode Control
Figure 48 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54060 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 47) is the power stage
transconductance. The gm_PS for the TPS54060 is 1.9A/V. The low-frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 48. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 17).
V_O
VC
R_ESR
gm_ps
C_OUT
Adc
fp
R_L
fz
Figure 48. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
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