TPS50301-HT_16 Datasheet, PDF (27/41 Pages) Texas Instruments – Input, 3-A/6-A Synchronous Step-Down SWIFT Converter

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TPS50301-HT
SLVSA94I – DECEMBER 2012 – REVISED JANUARY 2016
• R_ESR is the equivalent series resistance of the output capacitor.
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8.3.22 Small Signal Model for Frequency Compensation
The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly
used frequency compensation circuits shown in Figure 28. In Type 2A, one additional high-frequency pole is
added to attenuate high-frequency noise.
The following design guidelines are provided for advanced users who prefer to compensate using the general
method. The step-by-step design procedure described in Detailed Design Procedure may also be used.
VOUT
R1 _VSENSE
Vref
R2
gmea
Roea
COMP ^{Type 2A Type 2B}
R3 C2
R3
Coea
C1
C1
Figure 28. Types of Frequency Compensation
The general design guidelines for device loop compensation are as follows:
1. Determine the crossover frequency ƒc. A good starting point is one-tenth of the switching frequency, ƒ_SW.
2. R3 can be determined by:
R3 = ^{2p ´ ¦c ´ VOUT ´ Co}
g m_ea ´ Vre f ´ gm_ps
where
• gm_ea is the GM amplifier gain ( 1300 μA/V).
• gm_ps is the power stage gain (18 A/V).
• Vref is the reference voltage (0.795 V)
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3.
æ
ç
¦p
=
Place a compensation zero at the dominant pole ^è
C_O
´
1
R_L
´
ö
2p
÷
ø
.
C1 can be determined by
C1 = ^{RL ´ Co}
R3
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4. C2 is optional. It can be used to cancel the zero from the equivalent series resistance (ESR) of the output
capacitor Co.
C2 = ^{RESR ´ Co}
R3
(19)
NOTE
For PSpice models and WEBENCH design tool, see the Tools & Software tab.
1. PSpice average model (stability – bode plot)
2. PSpice transient model (switching waveforms)
3. WEBENCH design tool www.ti.com/product/TPS50301-HT/toolssoftware
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