TMS320C242_09 Datasheet, PDF (27/74 Pages) Texas Instruments – High-Performance Static CMOS Technology

TMS320C242
DSPĂCONTROLLER
SPRS063D − DECEMBER 1997 − REVISED SEPTEMBER 2000
clock domains (continued)
Two control bits, LPM(1) and LPM(0), specify which of the three possible low-power modes is entered when
the IDLE instruction is executed (see Table 7). These bits are located in the System Control and Status Register
(SCSR) described in the TMS320F243,F241,C242 DSP Controllers System and Peripherals User’s Guide
Volume 2 (literature number SPRU276).
LOW-POWER MODE
CPU running normally
Table 7. Low-Power Modes Summary
LPMx BITS
SCSR[13:12]
XX
CPU
CLOCK
DOMAIN
On
SYSTEM
CLOCK
DOMAIN
On
WDCLK
STATUS
On
PLL
STATUS
On
IDLE1 − (LPM0)
00
Off
On
On
On
OSC
STATUS
On
On
EXIT
CONDITION
—
Peripheral Interrupt,
External Interrupt,
Reset
IDLE2 − (LPM1)
Wakeup Interrupts,
01
Off
Off
On
On
On
External Interrupt,
Reset
HALT − (LPM2)
{PLL/OSC power down}
1X
Off
Off
Off
Off
Off
Reset Only
wakeup from low-power modes
reset
A reset (from any source) causes the device to exit any of the IDLE modes. If the device is halted, the reset will
first start the oscillator, and there can be a delay while the oscillator powers up before clocks are generated to
initiate the CPU reset sequence.
external interrupts
The external interrupts, XINTx, can cause the device to exit any of the low-power modes, except HALT. If the
device is in IDLE2 mode, the synchronous logic connected to the external interrupt pins is bypassed with
combinatorial logic which recognizes the interrupt on the pin, starts the clocks, and then allows the clocked logic
to generate an interrupt request to the PIE controller. Note that in Table 7, external interrupts include PDPINT.
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