TAS5066 Datasheet, PDF (27/64 Pages) Texas Instruments – SIX-CHANNEL Digital Audio PWM Processor

Architecture Overview
2.4.4 PWM DC-Offset Correction
An 8-bit value can be programmed to each of the six PWM offset correction registers to correct for any offset
present in the output stages. The offset correction is divided into 256 intervals with a total offset correction of
±1.56% of full scale. The default value is zero correction represented by 00 (hex). These values can be
changed at any time through the serial control interface.
2.4.5 Interchannel Delay
An 8-bit value can be programmed to each of the six PWM interchannel delay registers to add a delay per
channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.
Each subsequent channel has a default value that is N DCLKs larger than the preceding channel. The default
interchannel delay for the first channel and the interchannel delay between subsequent channels are mask
programmable. The present values are 0 for the first channel and increments of 53 for each successive
channel.
These values can be updated upon power up through the serial control interface. This delay is generated in
the PWM block with the appropriate control signals generated in the CTL block.
These values can be changed at any time through the serial control interface.
The optimum value for interchannel delay depends on the final system. This value can be adjusted for better
performance with regard to dynamic range and THD. It is recommended that the following TC delay values
be set instead of the default value. These TC delay values deliver the best performance in the test board.
REGISTER
0Ch
0Dh
0Eh
0Fh
10h
11h
SETTING
01h
49h
91h
39h
21h
69h
FUNCTION
TC delay channel 1
TC delay channel 2
TC delay channel 3
TC delay channel 4
TC delay channel 5
TC delay channel 6
These values must be reprogrammed every time RESET is asserted. RESET causes default values to be
loaded.
2.4.6 PWM/H-Bridge and Discrete H-Bridge Driver Interface
The TAS5066 provides six PWM outputs, which are designed to drive switching output stages (back-ends)
in both single-ended (SE) and H-bridge (bridge tied load) configuration. The back-ends may be monolithic
power stages (such as the TAS5110) or six discrete differential power stages using gate drivers (such as the
the TAS55182) and MOSFETs in single-ended or bridged configurations.
The TAS5110 device is optimized for bridge tied load (BTL) configurations. These devices require a pure
differential PWM signal with a third signal (VALID) to control the MUTE state. In the MUTE state, the TAS5110
OUTA and OUTB are both low.
One Channel
of TAS5066
TAS5110
PWM_AP
PWM_AM
VALID
AP
AM
RESET
BP
BM
OUTA
OUTB
Speaker
Figure 2−12. PWM Outputs and H-Bridge Driven in BTL Configuration
22 TAS5066
SLES089—January 2004