LMH6586 Datasheet, PDF (27/33 Pages) National Semiconductor (TI) – 32x16 Video Crosspoint Switch

LMH6586
www.ti.com
SNCS105D – JULY 2008 – REVISED MARCH 2013
Table 4. Video and Sync Detection Control Registers
Register
Address R/W
RESERVED
0x08h R/W
0x0Bh
VIDEO DETECT
INVERT (CH 0-7)
0x0Ch R/W
VIDEO DETECT
INVERT (CH 8-15)
0x0Dh R/W
VIDEO DETECT
0x0Eh R/W
INVERT (CH 16-23)
VIDEO DETECT
0x0Fh R/W
INVERT (CH 24-31)
SYNC DETECT
ENABLE (CH 0-7)
0x10h R/W
SYNC DETECT
0x11h R/W
ENABLE (CH 8-15)
SYNC DETECT
0x12h R/W
ENABLE (CH 16-23)
SYNC DETECT
0x13h R/W
ENABLE (CH 24-31)
VIDEO DETECT
ENABLE (CH 0-7)
0x14h R/W
VIDEO DETECT
0x15h R/W
ENABLE (CH 8-15)
VIDEO DETECT
0x16h R/W
ENABLE (CH 16-23)
VIDEO DETECT
0x17h R/W
ENABLE (CH 24-31)
Default
0x00
Bit 7
RSV
Bit 6
RSV
Bit 5
RSV
Bit 4
RSV
Bit 3
RSV
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
VD_
INV_7
VD_
INV_15
VD_
INV_23
VD_
INV_31
SD_
EN_7
SD_
EN_15
SD_
EN_23
SD_
EN_31
VD_
EN_7
VD_
EN_15
VD_
EN_23
VD_
EN_31
VD_
INV_6
VD_
INV_14
VD_
INV_22
VD_
INV_30
SD_
EN_6
SD_
EN_14
SD_
EN_22
SD_
EN_30
VD_
EN_6
VD_
EN_14
VD_
EN_22
VD_
EN_30
VD_
INV_5
VD_
INV_13
VD_
INV_21
VD_
INV_29
SD_
EN_5
SD_
EN_13
SD_
EN_21
SD_
EN_29
VD_
EN_5
VD_
EN_13
VD_
EN_21
VD_
EN_29
VD_
INV_4
VD_
INV_12
VD_
INV_20
VD_
INV_28
SD_
EN_4
SD_
EN_12
SD_
EN_20
SD_
EN_28
VD_
EN_4
VD_
EN_12
VD_
EN_20
VD_
EN_28
VD_
INV_3
VD_
INV_11
VD_
INV_19
VD_
INV_27
SD_
EN_3
SD_
EN_11
SD_
EN_19
SD_
EN_27
VD_
EN_3
VD_
EN_11
VD_
EN_19
VD_
EN_27
Bit 2
RSV
VD_
INV_2
VD_
INV_10
VD_
INV_18
VD_
INV_26
SD_
EN_2
SD_
EN_10
SD_
EN_18
SD_
EN_26
VD_
EN_2
VD_
EN_10
VD_
EN_18
VD_
EN_26
Bit 1
RSV
VD_
INV_1
VD_
INV_9
VD_
INV_17
VD_
INV_24
SD_
EN_1
SD_
EN_9
SD_
EN_17
SD_
EN_25
VD_
EN_1
VD_
EN_9
VD_
EN_17
VD_
EN_25
Bit 0
RSV
VD_
INV_0
VD_
INV_8
VD_
INV_16
VD_
INV_24
SD_
EN_0
SD_
EN_8
SD_
EN_16
SD_
EN_24
VD_
EN_0
VD_
EN_8
VD_
EN_16
SD_
EN_24
Register
VIDEO DETECT
THRESHOLD
Table 5. Video Detection Threshold Control Registers
Address R/W
0x1Dh R/W
Default
0x00
Bit 7
Bit 6
Bit 5
RSV
Bit 4
Bit 3
Bit 2
Bit 1
VDT[2:0]
Bit 0
Register
INPUT SHUTDOWN
(CH 0-7)
INPUT SHUTDOWN
(CH 8-15)
INPUT SHUTDOWN
(CH 16-23)
INPUT SHUTDOWN
(CH 24-31)
OUTPUT
SHUTDOWN
(CH 0-7)
OUTPUT
SHUTDOWN
(CH 8-15)
Address
0x18h
0x19h
0x1Ah
0x1Bh
0x1Eh
0x1Fh
Table 6. Input and Output Shutdown Registers
R/W Default Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
R/W 0x00
IN_
IN_
IN_
IN_
IN_
PS_7 PS_6 PS_5 PS_4 PS_3
R/W 0x00
IN_
IN_
IN_
IN_
IN_
PS_15 PS_14 PS_13 PS_12 PS_11
R/W 0x00
IN_
IN_
IN_
IN_
IN_
PS_23 PS_22 PS_21 PS_20 PS_19
R/W 0x00
IN_
IN_
IN_
IN_
IN_
PS_31 PS_30 PS_29 PS_28 PS_27
R/W 0x00 OUT_ OUT_ OUT_ OUT_ OUT_
PS_7 PS_6 PS_5 PS_4 PS_3
R/W 0x00 OUT_ OUT_ OUT_ OUT_ OUT_
PS_15 PS_14 PS_13 PS_12 PS_11
Bit 2
IN_
PS_2
IN_
PS_10
IN_
PS_18
IN_
PS_26
OUT_
PS_2
OUT_
PS_10
Bit 1
IN_
PS_1
IN_
PS_9
IN_
PS_17
IN_
PS_25
OUT_
PS_1
OUT_
PS_9
Bit 0
IN_
PS_0
IN_
PS_8
IN_
PS_16
IN_
PS_24
OUT_
PS_0
OUT_
PS_8
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