LM3S9DN6 Datasheet, PDF (27/1388 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S9DN6 Microcontroller
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 685
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 685
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 685
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 685
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 685
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 688
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 688
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 688
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 688
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 688
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 688
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 688
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 688
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 690
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 705
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 707
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 710
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 713
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 714
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 715
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 716
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 718
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 722
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 724
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 728
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 732
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 736
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 738
Register 15: UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 739
Register 16: UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 740
Register 17: UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 741
Register 18: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 742
Register 19: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 743
Register 20: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 744
Register 21: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 745
Register 22: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 746
Register 23: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 747
Register 24: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 748
Register 25: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 749
Register 26: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 750
Register 27: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 751
Register 28: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 752
Register 29: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 753
Synchronous Serial Interface (SSI) ............................................................................................ 754
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 769
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 771
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 773
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 774
January 23, 2012
27
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