LM3S6618 Datasheet, PDF (27/689 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S6618 Microcontroller
Table 1. Revision History (continued)
Date
October 2009
Revision Description
6462 ■ Deleted MAXADCSPD bit field from DCGC0 register as it is not applicable in Deep-Sleep mode.
■ Removed erroneous reference to the WRC bit in the Hibernation chapter.
■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
■ Clarified PWM source for ADC triggering.
■ Made these changes to the Electrical Characteristics chapter:
– Removed V_SIH and V_SIL parameters from Operating Conditions table.
– Added table showing actual PLL frequency depending on input crystal.
– Changed the name of the t_{HIB_REG_WRITE} parameter to t_{HIB_REG_ACCESS}.
– Revised ADC electrical specifications to clarify, including reorganizing and adding new data.
– Changed SSI set up and hold times to be expressed in system clocks, not ns.
July 2009
July 2009
5920
5902
Corrected ordering numbers.
■ Clarified Power-on reset and RST pin operation; added new diagrams.
■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)
registers.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
■ Added description for Ethernet PHY power-saving modes.
■ Corrected the reset values for bits 6 and 7 in the Ethernet MR24 register.
■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.
■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added E_IR
(Internal voltage reference error) parameter.
■ Additional minor data sheet clarifications and corrections.
April 2009
5367
■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 162).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Added "GPIO Module DC Characteristics" table (see Table 20-4 on page 636).
■ Additional minor data sheet clarifications and corrections.
January 2009
4660
■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Added "Hardware Configuration" section to Ethernet Controller chapter.
■ Additional minor data sheet clarifications and corrections.
June 19, 2012
27
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