LM12454 Datasheet, PDF (27/43 Pages) National Semiconductor (TI) – 12-Bit Sign Data Acquisition System with Self-Calibration

LM12454, LM12458, LM12H458
www.ti.com
SNAS079A – MAY 2004 – REVISED FEBRUARY 2006
Table 1. LM12(H)454/8 Memory Map for 16-Bit Wide Data Bus (BW = “0”, Test Bit = “0” and A0 = Don't Care)
A4
A3
A2
A1 Purpo Type D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
se
0
0
0 Instruc
0
to
tion
RAM
(RAM
R/W
1
1
1 Pointe
r = 00)
Acquisition Time
Watch
- dog
8/12
Timer Sync
V_IN− (MUXOUT−) ⁽¹⁾
V_IN+ (MUXOUT+) ⁽¹⁾ Pause Loop
0
0
0 Instruc
0
1
to
1
tion
1
RAM
(RAM
R/W
Pointe
r = 01)
Don't Care
>/< Sign
Limit #1
0
0
0 Instruc
0
1
to
1
tion
1
RAM
(RAM
R/W
Pointe
r = 10)
Don't Care
>/< Sign
Limit #2
Config
1
0
0
0
uration
Regist
R/W
er
Don't Care
DIAG * Test =
(2)
0
RAM Pointer
i/O Sel
Auto
Zero_ec
Char Stand-
Mask by
Full
CAL
Auto-
Zero
Reset
Start
Interru
1
0
0
1
pt
Enable R/W
Regist
Number of Conversions in Conversion
FIFO to Generate INT2
Sequencer Address to
Generate INT1
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
er
Interru
1
0
1
pt
0 Status R
Regist
Actual Number of Conversion Results in
Conversion FIFO
Address of Sequencer
Instruction being
INST7 INST6 INST5 INST4 INST3 INST2 INST1 INST0
Executed
er
Timer R/W
1
0
1
1 Regist
er
Timer Preset High Byte
Timer Preset Low Byte
Conve
1
1
0
0 rsion R
FIFO
Address or Sign
Sign
Conversion Data: MSBs
Conversion Data: LSBs
Limit
1
1
0
1
Status
Regist
R
er
Limit #2: Status
Limit #1: Status
(1) LM12454 (Refer to Table 4).
(2) LM12(H)458 only. Must be set to “0” for the LM12454.
Copyright © 2004–2006, Texas Instruments Incorporated
Product Folder Links: LM12454 LM12458 LM12H458
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