ADS8684A Datasheet, PDF (27/80 Pages) Texas Instruments – 4- and 8-Channel, Single-Supply, SAR ADCs

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ADS8684A, ADS8688A
SBAS680 – JULY 2015
8.3.4 Programmable Gain Amplifier (PGA)
The devices offer a programmable gain amplifier (PGA) at each individual analog input channel, which converts
the original single-ended input signal into a fully-differential signal to drive the internal 16-bit ADC. The PGA also
adjusts the common-mode level of the input signal before being fed into the ADC to ensure maximum usage of
the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be accordingly
adjusted by setting the Range_CHn[3:0] (n = 0 to 3 or 7) bits in the program register. The default or power-on
state for the Range_CHn[3:0] bits is 0000, which corresponds to an input signal range of ±2.5 × V_REF. Table 3
lists the various configurations of the Range_CHn[3:0] bits for the different analog input voltage ranges.
The PGA uses a very highly-matched network of resistors for multiple gain configurations. Matching between
these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain error low
across all channels and input ranges.
Table 3. Input Range Selection Bits Configuration
ANALOG INPUT RANGE
±2.5 × V_REF
±1.25 × V_REF
±0.625 × V_REF
±0.3125 × V_REF
±0.15625 × V_REF
0 to 2.5 × V_REF
0 to 1.25 × V_REF
0 to 0.625 × V_REF
0 to 0.3125 × V_REF
BIT 3
0
0
0
0
1
0
0
0
1
Range_CHn[3:0]
BIT 2
BIT 1
0
0
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
1
BIT 0
0
1
0
1
1
1
0
1
1
8.3.5 Second-Order, Low-Pass Filter (LPF)
In order to mitigate the noise of the front-end amplifiers and gain resistors of the PGA, each analog input channel
of the ADS8684A and ADS8688A features a second-order, antialiasing LPF at the output of the PGA. The
magnitude and phase response of the analog antialiasing filter are shown in Figure 71 and Figure 72,
respectively. For maximum performance, the –3-dB cutoff frequency for the antialiasing filter is typically set to
15 kHz. The performance of the filter is consistent across all input ranges supported by the ADC.
2
1
0
±1
±2
±3
---- ± 2.5*V_REF, ---- “ 1.25*V_REF
±4
---- “ 0.625*V_REF, ------“0.3125*V_REF
-------“0.156 V_REF, ---- + 2.5*V_REF
±5
---- + 1.25*V_REF, ---- + 0.625*V_REF
---- + 0.3125*V_REF
±6
100
1000
Input Frequency (Hz)
10000
C064
0
±15
±30
±45
±60 _{---- ± 2.5*VREF, ---- “ 1.25*VREF}
---- “ 0.625*V_REF, ------“0.3125*V_REF
±75 ^{-------“0.156 V}REF, ^{---- + 2.5*V}REF
---- + 1.25*V_REF, ---- + 0.625*V_REF
---- + 0.3125*V_REF
±90
100
1000
Input Frequency (Hz)
10000
C065
Figure 71. Second-Order LPF Magnitude Response
Figure 72. Second-Order LPF Phase Response
Copyright © 2015, Texas Instruments Incorporated
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