LM3S1H16 Datasheet, PDF (261/805 Pages) Texas Instruments – Stellaris® LM3S1H16 Microcontroller

Stellaris^® LM3S1H16 Microcontroller
6.3
6.3.1
6.3.2
Functional Description
The Hibernation module provides two mechanisms for power control:
■ The first mechanism controls the power to the microcontroller with a control signal (HIB) that
signals an external voltage regulator to turn on or off.
■ The second mechanism uses internal switches to control power to the Cortex-M3 as well as to
most analog and digital functions while retaining I/O pin power (VDD3ON mode).
The Hibernation module power source is determined dynamically. The supply voltage of the
Hibernation module is the larger of the main voltage source (V_DD) or the battery/auxilliary voltage
source (V_BAT). The Hibernation module also has an independent clock source to maintain a real-time
clock (RTC) when the system clock is powered down.
Once in hibernation, the module signals an external voltage regulator to turn the power back on
when an external pin (WAKE) is asserted or when the internal RTC reaches a certain value. The
Hibernation module can also detect when the battery voltage is low and optionally prevent hibernation
when this occurs.
When waking from hibernation, the HIB signal is deasserted. The return of V_DD causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (t_{WAKE_TO_HIB}) plus the power-on reset time (T_IRPOR).
Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is t_{HIB_REG_ACCESS}, therefore
software must guarantee that this delay is inserted between back-to-back writes to certain Hibernation
registers or between a write followed by a read to those same registers. Software may make use
of the WRC bit in the Hibernation Control (HIBCTL) register to ensure that the required timing gap
has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to
software that another write or read may be started safely. Software should poll HIBCTL for WRC=1
prior to accessing any affected register. The following registers are subject to this timing restriction:
■ Hibernation RTC Counter (HIBRTCC)
■ Hibernation RTC Match 0 (HIBRTCM0)
■ Hibernation RTC Match 1 (HIBRTCM1)
■ Hibernation RTC Load (HIBRTCLD)
■ Hibernation RTC Trim (HIBRTCT)
■ Hibernation Data (HIBDATA)
Back-to-back reads from Hibernation module registers have no timing restrictions. Reads are
performed at the full peripheral clock rate.
Hibernation Clock Source
In systems where the Hibernation module is used to put the microcontroller into hibernation, the
module must be clocked by an external source that is independent from the main system clock,
even if the RTC feature is not used. An external oscillator or crystal is used for this purpose. To use
a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is
January 23, 2012
261
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