TPSM846C23_17 Datasheet, PDF (26/82 Pages) Texas Instruments – 4.5-V to 15-V Input, 0.35-V to 2.0-V Output, 35-A PMBus Power Module

TPSM846C23
SLVSDF3C – MARCH 2017 – REVISED AUGUST 2017
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7.3.21 Overtemperature Protection
An internal temperature sensor based off the bandgap reference protects the TPSM846C23 device from thermal
runaway. The internal thermal shutdown threshold, T_SD, is fixed at 145°C (typical), which is different from the
user programmable OT_FAULT_LIMIT. When the device senses a temperature above T_SD, an otf_bg bit in the
STATUS_MFR_SPECIFIC command is flagged, and power conversion stops until the sensed junction
temperature decreases by the amount of the thermal shutdown hysteresis, T_HYST (20°C typical). The SMBALERT
signal is triggered if the signal is not masked.
The device response to an OT_FAULT_LIMIT event can be set to Latch-off, Restart and Ignore in
OT_FAULT_RESPONSE. The default response to an over temperature fault is to shut down and then restart.
Fixed band gap-detected overtemperature (OT) faults are never ignored. The band gap OT faults always
respond in a shutdown and attempted restart once the part cools. Table 6 summarizes the fault-response
scheme.
7.3.22 Overcurrent Protection
Both low-side overcurrent and high-side short circuit protection are implemented. The low-side overcurrent fault
and warning thresholds are programmed via PMBus. The low-side MOSFET average current is compared to the
set fault threshold. High-side pulses are terminated on a cycle-by-cycle basis whenever the current through the
high-side MOSFET exceeds the fixed short circuit threshold.
When either a low-side overcurrent or high-side short circuit threshold is exceeded in a switching cycle, a counter
is incremented. If no overcurrent condition is detected in a switching cycle, the counter is decremented. When
the counter counts to three, an overcurrent fault condition is declared and the output shuts down and restarts
after 7 x TON_RISE time or is latched off until re-enabled, or ignored depending on the fault response setting.
The behavior of the power stage during the various fault scenarios is shown in Table 6.
7.3.23 Output Overvoltage and Undervoltage Protection
The TPSM846C23 device includes both output overvoltage protection and output undervoltage protection
capability by comparing the FB pin voltage to internal selectable pre-set voltages, as defined by the
PCT_OV_UV_WRN_FLT_LIMITS (MFR_SPECIFIC_07) (D7h) command.
If the FB pin voltage rises above the output overvoltage protection threshold, the device terminates normal
switching and turns on the low-side MOSFET to discharge the output capacitor and prevent further increases in
the output voltage. The device also declares an OV fault, flagging the appropriate status registers, triggering
SMBALERT if it is not masked. Then the device enters continuous-restart-hiccup mode or latches off according
to the VOUT_OV_FAULT_RESPONSE command. The TPSM846C23 device responds to the output Overvoltage
condition immediately upon VIN powered up and BP6 regulator voltage above its own UVLO of 3.73 V (typical).
The VOUT_OV_FAULT_RESPONSE can also be set to ignore the output overvotlage fault and continue without
interruption. Under this configuration, the control loop continues to respond and adjust PWM duty cycle to keep
output voltage within regulation.
If the FB pin voltage falls below the Undervoltage protection level after soft-start has completed, the device
terminates normal switching and forces both the high-side and low-side MOSFETs off, and awaits an external
reset or begins a hiccup time-out delay prior to restart, depending on the value of the
VOUT_UV_FAULT_RESPONSE command. The device also declares a UV fault by flagging the appropriate
status registers and triggering SMBALERT if it is not masked. The VOUT_UV_FAULT_RESPONSE can also be
set to ignore the output undervoltage fault and continue without interruption for debug purpose.
The TPSM846C23 device also provides FB referred fixed threshold (2.2 V typical) output overvoltage protection.
Table 6 summarizes the fault-response scheme.
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