TPS54260-Q1 Datasheet, PDF (26/48 Pages) Texas Instruments – 3.5 V to 60 V STEP DOWN CONVERTER WITH ECO-MODE™

TPS54260-Q1
SLVSAH8A – DECEMBER 2010 – REVISED APRIL 2011
DETAILED DESCRIPTION (continued)
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COMP
c
R3
C2
C1
Power Stage
gm_ps 10.5 A/V
PH
V_O
a
b
R1
R_ESR
R_L
CO RO
0.8 V
gm_ea
310 mA/V
VSENSE
R2
C_OUT
Figure 46. Small Signal Model for Loop Response
Simple Small Signal Model for Peak Current Mode Control
Figure 47 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54260-Q1 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 46) is the power stage
transconductance. The gm_PS for the TPS54260-Q1 is 10.5 A/V. The low-frequency gain of the power stage
frequency response is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 47. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 17).
V_O
VC
R_ESR
gm_ps
C_OUT
Adc
fp
R_L
fz
Figure 47. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
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