TMS320VC5471_16 Datasheet, PDF (26/102 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

DSP Subsystem Functional Overview
3.2.5 DSP Extended Program Memory
The DSP subsystem includes a memory paging scheme to extend the number of addressable program space
locations from 64K to 1M words. The four extended address pins (DSP_A16 to DSP_A19) are used to address
15 pages of program memory. Each page includes 64K addressable locations. The extended program
addresses are supported by eight instructions: FB[D], FBACC[D], FCALA[D], FCALL[D], FRET[D],
FRETE[D], READA, and WRITA.
• FB[D] – Far branch
• FBACC[D] – Far branch to the location specified by the value in accumulator A or accumulator B
• FCALA[D] – Far call to the location specified by the value in accumulator A or accumulator B
• FCALL[D] – Far call
• FRET[D] – Far return
• FRETE[D] – Far return with interrupts enabled
• READA – Read program memory addressed by accumulator A and store in data memory
• WRITA – Write data to program memory addressed by accumulator A
For more information on these instructions, please refer to the TMS320C54x DSP Reference Set, Volume 2:
Mnemonic Instruction Set (literature number SPRU172).
When the OVLY bit is set, each page of program memory is made up of two parts: a common block of
24K words maximum and a unique block of 40K words minimum. The common block is shared by all pages,
and each unique block is accessible only through its assigned page.
The value of the program counter extension register (XPC) defines the page selection. At a hardware reset,
the XPC is initialized to 0.
0 0000
1 0000
Page 1
2 0000
Page 2
...
Lower 24K^†
Lower 24K^†
1 5FFF ^External
2 5FFF ^External
...
1 6000
2 6000
Page 0
64K
Page 1
Upper 40K
External
Page 2
...
Upper 40K
External
...
0 FFFF
1 FFFF
2 FFFF
F 0000
F 5FFF
F 6000
Page 15
Lower 24K^†
External
Page 15
Upper 40K
External
F FFFF
† _{Accesses to the lower 24K words of pages 1 through 15 are to external program memory only when the OVLY bit is cleared to 0. If the OVLY bit}
is set to 1, on-chip RAM is mapped to 0x0 to 0x5FFF of pages 1 through 15. Note external address pins are provided to support 15 external pages.
Figure 3--4. DSP Extended Program Memory Map
3.2.6 DSP Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning
that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes
the code at the vector location. Four words are reserved at each vector location to accommodate a delayed
branch instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the
appropriate interrupt service routine with minimal overhead.
16 SPRS180C
June 2001 - Revised December 2002