THS4032-EP Datasheet, PDF (26/38 Pages) Texas Instruments – 100-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS

THS4031-EP
THS4032-EP
SLOS610 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
CIRCUIT-LAYOUT CONSIDERATIONS
In order to achieve the levels of high-frequency performance of the THS403x, it is essential that proper
printed-circuit board (PCB) high-frequency design techniques be followed. A general set of guidelines is given
below. In addition, a THS403x evaluation board is available to use as a guide for layout or for evaluating the
device performance.
• Ground planes: It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power-supply decoupling: Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inch between the device power terminals and the ceramic capacitors.
• Sockets: Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance
in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the
printed-circuit board is the best implementation.
• Short trace runs/compact part placements: Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
• Surface-mount passive components: Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
GENERAL PowerPAD™ DESIGN CONSIDERATIONS
The THS403x is available in a thermally-enhanced DGN package, which is a member of the PowerPAD family of
packages. This package is constructed using a downset leadframe upon which the die is mounted [see
Figure 60(a) and Figure 60(b)]. This arrangement results in the leadframe being exposed as a thermal pad on
the underside of the package [see Figure 60(c)]. Because this thermal pad has direct thermal contact with the
die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal
pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the heretofore awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
A. The thermal pad is electrically isolated from all terminals in the package.
Figure 60. Views of Thermally-Enhanced DGN Package
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