TAS5733L Datasheet, PDF (26/68 Pages) Texas Instruments – Digital Input Audio Power Amplifier

TAS5733L
SLASE77A – MARCH 2016 – REVISED MARCH 2016
www.ti.com
Programming (continued)
7.6.2.3 Left-Justified
Left-justified (LJ) timing uses LRCK to define when the data being transmitted is for the left channel and when
the data is for the right channel. LRCK is high for the left channel and low for the right channel. A bit clock
running at 32 × f_S, 48 × f_S, or 64 × f_S is used to clock in the data. The first bit of data appears on the data lines at
the same time LRCK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The
DAP masks unused trailing data bit positions.
2-Channel Left-Justified Stereo Input
LRCLK
32 Clks
Left Channel
32 Clks
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
98
20-Bit Mode
19 18
54
16-Bit Mode
15 14
10
54
10
10
LSB MSB
23 22
98
54
19 18
54
10
15 14
10
NOTE: All data presented in two's-complement form with MSB first.
Figure 40. Left-Justified 64-f_S Format
10
LSB
T0034-02
26
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