PCM9211_16 Datasheet, PDF (26/125 Pages) Texas Instruments – Digital Audio Interface Transceiver

PCM9211
SBAS495A – JUNE 2010 – REVISED JANUARY 2016
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8.3.8.5.14 ADC Level Detect and Interrupt
The PCM9211 has the ability to monitor audio inputs, which can be used to trigger interrupt outputs on port INT1.
The ADC has a level monitor that can be set so that INT1 can be triggered whenever a specific level (referenced
to 0dBFS) is crossed. A block diagram for this function is shown in Figure 19.
ADC Core
24
MainPort/MPIO
Matrix
MainPort/
MPIOs
DIR Core
Level
Detector
INT
8
REG
ERROR
NPCM
EMPH
DTSCD
CSRNW
PCRNW
FSCHG
7
ADDTLV[1:0]
ERROR/
NPCM
ERROR ₂
NPCM
Figure 19. Block Diagram for ADC Level Detection
SPI/I2C
ERROR/INT0
NPCM/INT1
Operation of the level detect circuitry is shown in Figure 20. The ADC level detect is flagged when either ADC
channel goes high. The flag is cleared when Register 2Dh is read.
VINL
VINR
LVL DET Flag
NPCM/INT1 pin
Register 2Dh_B0
SPI/I²C
Read Register 2Dh
Figure 20. Operation of the ADC Level Detect Circuitry
The trigger threshold for the ADC can be configured at four different levels below full scale using the
ADLVLTH[1:0] bits in Register 2Eh. The output is post-ADC volume control, allowing finer gain steps to be
configured by changing the ADC volume control.
In a typical application, this level change is done as the system moves into standby, and reset back to 0dB
attenuation when the system wakes up.
The output of this comparator circuit can be ORed along with the INT1 interrupt that is sourced. When the INT1
interrupt is flagged, then the INT1 output register can be read by the host controller.
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