LMR23625-Q1_16 Datasheet, PDF (26/37 Pages) Texas Instruments – SIMPLE SWITCHER 36 V, 2.5 A Synchronous Step-Down Converter

LMR23625-Q1
SNVSAR5 – DECEMBER 2016
www.ti.com
11.3 Ground Plane and Thermal Considerations
It is recommended to use one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and
PGND pins should be connected to the ground plane using vias right next to the bypass capacitors. PGND pin is
connected to the source of the internal LS switch. They should be connected directly to the grounds of the input
and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load
variations. PGND trace, as well as VIN and SW traces, should be constrained to one side of the ground plane.
The other side of the ground plane contains much less noise and should be used for sensitive routes.
It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal
path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane heat
sink. The vias should be evenly distributed under the PAD. Use as much copper as possible, for system ground
plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper
thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough
copper thickness provides low current conduction impedance, proper shielding and lower thermal resistance.
The thermal characteristics of the LMR23625-Q1 are specified using the parameter θ_JA, which characterize the
junction temperature of silicon to the ambient temperature in a specific system. Although the value of θ_JA is
dependent on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use the following relationship:
T_J = P_D x θ_JA + T_A
(22)
where
T_J = Junction temperature in °C
P_D = V_IN x I_IN x (1 - Efficiency) - 1.1 x I_OUT2 x DCR in Watt
DCR = Inductor DC parasitic resistance in Ω
θ_JA = Junction to ambient thermal resistance of the device in °C/W
T_A = Ambient temperature in °C
The maximum operating junction temperature of the LMR23625-Q1 is 125 °C. θ_JA is highly related to PCB size
and layout, as well as environmental factors such as heat sinking and air flow.
11.4 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and
C_FF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider and C_FF closer to the FB pin reduces the
trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace
from V_OUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so will correct
for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider should be routed away from the SW node path and the inductor to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. It is recommended to route the voltage
sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that
there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further
shielding for the voltage feedback path from EMI noises.
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